[rocketv] change icache axi width blockBytes -> fetchBytes.

chipsalliance · Nov 18, 2024 · be3385d · be3385d
1 parent fb6ecc7
commit be3385d
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Showing 2 changed files with 10 additions and 5 deletions.
diff --git a/rocketv/src/Frontend.scala b/rocketv/src/Frontend.scala
@@ -113,7 +113,7 @@ case class FrontendParameter(
     exec = exec,
     sideEffects = sideEffects
   )
-  val rowBits:                   Int                 = blockBytes * 8
+  val rowBits:                   Int                 = fetchBytes * 8
   val instructionFetchParameter: AXI4BundleParameter = AXI4BundleParameter(
     idWidth = 1,
     dataWidth = rowBits,

diff --git a/rocketv/src/ICache.scala b/rocketv/src/ICache.scala
@@ -41,7 +41,7 @@ case class ICacheParameter(
   val hasUncorrekoctable:        Boolean                     = itimBaseAddr.nonEmpty && dataCode.canDetect
   val isDM:                      Boolean                     = nWays == 1
   // axi data with
-  val rowBits:                   Int                         = blockBytes * 8
+  val rowBits:                   Int                         = fetchBytes * 8
   val refillCycles:              Int                         = blockBytes * 8 / rowBits
   val blockOffBits:              Int                         = log2Up(blockBytes)
   val idxBits:                   Int                         = log2Up(nSets)
@@ -542,8 +542,13 @@ class ICache(val parameter: ICacheParameter)
   for ((data_array, i) <- icacheDataSRAM.zipWithIndex) {
 
     /** bank match (vaddr[2]) */
-    def wordMatch(addr: UInt): Bool =
-      addr(log2Ceil(io.instructionFetchAXI.r.bits.data.getWidth / 8) - 1, log2Ceil(wordBits / 8)) === i.U
+    def wordMatch(addr: UInt): Bool = {
+      if (io.instructionFetchAXI.r.bits.data.getWidth == wordBits) { true.B }
+      else {
+        addr(log2Ceil(io.instructionFetchAXI.r.bits.data.getWidth / 8) - 1, log2Ceil(wordBits / 8)) === i.U
+      }
+    }
+
     // TODO: if we have last? do we need refillCycles?
     def row(addr: UInt) = addr(untagBits - 1, blockOffBits - log2Ceil(refillCycles))
 
@@ -792,7 +797,7 @@ class ICache(val parameter: ICacheParameter)
   arQueue.enq.bits.id    := 0.U
   arQueue.enq.bits.addr  := (refill_paddr >> blockOffBits) << blockOffBits
   arQueue.enq.bits.size  := log2Up(parameter.blockBytes).U
-  arQueue.enq.bits.len   := 0.U
+  arQueue.enq.bits.len   := (parameter.blockBytes * 8 / parameter.instructionFetchParameter.dataWidth - 1).U
   arQueue.enq.bits.burst := 1.U
   io.instructionFetchAXI.ar <> arQueue.deq