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[rtl] resolve comments
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Lucas-Wye committed Feb 6, 2024
1 parent 08e1d06 commit bc1b057
Showing 1 changed file with 46 additions and 48 deletions.
94 changes: 46 additions & 48 deletions t1/src/decoder/Decoder.scala
Original file line number Diff line number Diff line change
Expand Up @@ -36,57 +36,55 @@ trait BoolField extends BoolDecodeField[Op] with FieldName {
case class SpecialAux(name: String, vs: Int, value: String)
case class SpecialMap(name: String, vs: Int, data: Map[String, String])
case class SpecialAuxInstr(instrName: String, vs: Int, value: String, name: String)
case class Op(tpe: String, funct6: String, funct3: String,
case class Op(tpe: String, funct6: String, tpeOp2: String, funct3: String,
name: String, special: Option[SpecialAux], notLSU: Boolean) extends DecodePattern {
val funct3Map: Map[String, String] = Map(
"IV" -> "000",
"IX" -> "100",
"II" -> "011",
"MV" -> "010",
"MX" -> "110",
"FV" -> "001",
"FF" -> "101"
)

// include 21 bits: funct6 + vm + vs2 + vs1 + funct3 + LSU
def bitPat: BitPat = if (notLSU) BitPat(
"b" +
// funct6
funct6 +
// TODO[0]: ? for vm
// ? for vm
"?" +
// vs2
(if (special.isEmpty || special.get.vs == 1) "?????" else special.get.value) +
// vs1
(if (special.isEmpty || special.get.vs == 2) "?????" else special.get.value) +
// funct3
funct3Map(tpe + funct3) + "1"
funct3 + "1"
) else BitPat("b" + funct6 + "?" * 14 + "0")
}

object Decoder {
private val opVOpcode = "1010111"
private val loadFPOpcode = "0000111"
private val storeFPOpcode = "0100111"

private val opivvFunct3 = "000"
private val opiviFunct3 = "011"
private val opivxFunct3 = "100"
private val opmvvFunct3 = "010"
private val opmvxFunct3 = "110"
private val opfvvFunct3 = "001"
private val opfvfFunct3 = "101"
// Opcode: instruction[6:0]
// refer to [https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-instruction-formats]
private val opcodeV = "1010111"
private val opcodeLoadF = "0000111"
private val opcodeStoreF = "0100111"

// Funct3: instruction[14:12]
// refer to [https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#101-vector-arithmetic-instruction-encoding]
private val funct3IVV = "000"
private val funct3IVI = "011"
private val funct3IVX = "100"
private val funct3MVV = "010"
private val funct3MVX = "110"
private val funct3FVV = "001"
private val funct3FVF = "101"
private val funct3CFG = "111" // TODO: need implementations

// type of rs1
private val op1iFunct3 = Seq(opivvFunct3, opiviFunct3, opivxFunct3)
private val op1mFunct3 = Seq(opmvvFunct3, opmvxFunct3)
private val op1fFunct3 = Seq(opfvvFunct3, opfvfFunct3)
private val op1iFunct3 = Seq(funct3IVV, funct3IVI, funct3IVX)
private val op1mFunct3 = Seq(funct3MVV, funct3MVX)
private val op1fFunct3 = Seq(funct3FVV, funct3FVF)
private val op1cFunct3 = Seq(funct3CFG)
// type of rs2
private val op2vFunct3 = Seq(opivvFunct3, opmvvFunct3, opfvvFunct3)
private val op2xFunct3 = Seq(opivxFunct3, opmvxFunct3)
private val op2iFunct3 = Seq(opiviFunct3)
private val op2fFunct3 = Seq(opfvfFunct3)
private val op2vFunct3 = Seq(funct3IVV, funct3MVV, funct3FVV)
private val op2xFunct3 = Seq(funct3IVX, funct3MVX)
private val op2iFunct3 = Seq(funct3IVI)
private val op2fFunct3 = Seq(funct3FVF)

// special instrctions
// refer to [https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc]
private val insnVRXUNARY0 = SpecialMap("VRXUNARY0", 2, Map("vmv.s.x" -> "00000"))
private val insnVWXUNARY0 = SpecialMap("VWXUNARY0", 1, Map(
"vmv.x.s" -> "00000",
Expand Down Expand Up @@ -166,20 +164,19 @@ object Decoder {
i.name match {
// csr instructions
case s if Seq("vsetivli", "vsetvli", "vsetvl").contains(s) => false
// conflict instrctions `vmv` and `vmerge`, as defined in `riscv-v-spec/inst-table.adoc`
// conflict instrctions `vmv` and `vmerge`, as defined in [https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc]
case s if s.contains("vmv.v") => false
// conflict instructions `vfmv.v.f` and `vfmerge.vfm`, as defined in `riscv-v-spec/inst-table.adoc`
// conflict instructions `vfmv.v.f` and `vfmerge.vfm`, as defined in [https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc]
case s if s.contains("vfmv.v.f") => false
case _ => true
}
}.toSeq.distinct
// case of notLSU instructions
val expandedOps: Array[Op] = (instructions.filter(_.encoding.toString.substring(32-6-1, 32-0) == opcodeV).map{ insn =>
val funct3 = insn.encoding.toString.substring(32-14-1, 32-12)


val expandedOps: Array[Op] = (instructions.filter(_.encoding.toString.substring(32-6-1, 32-0) == opVOpcode).map{ insn =>
val realFunct3 = insn.encoding.toString.substring(32-14-1, 32-12)

val tpe = if (op1iFunct3.contains(realFunct3)) "I" else if (op1mFunct3.contains(realFunct3)) "M" else if (op1fFunct3.contains(realFunct3)) "F" else ""
val funct3 = if (op2vFunct3.contains(realFunct3)) "V" else if (op2xFunct3.contains(realFunct3)) "X" else if (op2iFunct3.contains(realFunct3)) "I" else if (op2fFunct3.contains(realFunct3)) "F" else ""
val tpe = if (op1iFunct3.contains(funct3)) "I" else if (op1mFunct3.contains(funct3)) "M" else if (op1fFunct3.contains(funct3)) "F" else "" // TODO: OPCFG
val tpeOp2 = if (op2vFunct3.contains(funct3)) "V" else if (op2xFunct3.contains(funct3)) "X" else if (op2iFunct3.contains(funct3)) "I" else if (op2fFunct3.contains(funct3)) "F" else "" // TODO: OPCFG
val funct6 = insn.encoding.toString.substring(32-31-1, 32-26)
val special = insnSpec.collectFirst { case s if (insn.name.contains(s.instrName)) => SpecialAux(s.name, s.vs, s.value) }
val name = special match {
Expand All @@ -189,20 +186,21 @@ object Decoder {
.replace(".wx", ".w").replace(".wv", ".w")
// replace `wf` for instructions `vfwsub.wf`
.replace(".wf", ".w")
// `vnsrl` is not in the above class
// deal with `vnsrl`
.replace("vnsrl.w", "vnsrl")

// remove '.m' of special instructions
case _ => insn.name.replace(".m", "")
}
Op(tpe, funct6, funct3, name, special, notLSU=true)
Op(tpe, funct6, tpeOp2, funct3, name, special, notLSU=true)
}
// case of `loadFPOpcode` and `storeFPOpcode`
// case of LSU instructions: `opcodeLoadF` and `opcodeStoreF`
++ Seq("1", "0").map(fun6End =>
Op(
"I",
"I", // tpe
"?????" + fun6End,
"???",
"?", // tpeOp2
"???", // funct3
"lsu",
None,
notLSU = false
Expand Down Expand Up @@ -442,8 +440,8 @@ object Decoder {
}

object nr extends BoolField {
// `vmv<nr>r` is replaced by instructions `vmv1r.v`,`vmv2r.v`, `vmv4r.v`, `vmv8r.r`
def value(op: Op): Boolean = op.name.contains("r.v")
// for instructions `vmv1r.v`,`vmv2r.v`, `vmv4r.v`, `vmv8r.v`
def value(op: Op): Boolean = Seq("vmv1r.v","vmv2r.v", "vmv4r.v", "vmv8r.v").contains(op.name)
}

object red extends BoolField {
Expand Down Expand Up @@ -523,11 +521,11 @@ object Decoder {
}

object vtype extends BoolField {
def value(op: Op): Boolean = op.funct3 == "V"
def value(op: Op): Boolean = op.tpeOp2 == "V"
}

object itype extends BoolField {
def value(op: Op): Boolean = op.funct3 == "I"
def value(op: Op): Boolean = op.tpeOp2 == "I"
}

object targetRd extends BoolField {
Expand Down

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