[tests] remove -riscv-v-vector-bits-min argument

According to LLVM source code, llc will automatically use zvl length when this argument not specify. https://llvm.org/doxygen/RISCVSubtarget_8cpp_source.html Signed-off-by: Avimitin <[email protected]>
chipsalliance · Aug 30, 2024 · b50ecf9 · b50ecf9
1 parent 919700e
commit b50ecf9
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/tests/pytorch/default.nix b/tests/pytorch/default.nix
@@ -53,7 +53,6 @@ let
                   -mtriple=riscv32 \
                   -target-abi=ilp32f \
                   -mattr=+m,+f,+zve32f \
-                  -riscv-v-vector-bits-min=128 \
                   --filetype=obj \
                   -o "$llvmir.o"