[difftest] refactor to pass cargo clippy

[difftest] use data instead of wrong _data

difftest/t1-simulator/src/difftest/dut.rs

@@ -122,6 +122,6 @@ impl Dut {
     };
     self.idx += 1;
 
-    return Ok(event);
+    Ok(event)
   }
 }

difftest/t1-simulator/src/difftest/spike.rs

@@ -19,7 +19,6 @@ use spike_event::*;
 
 use super::dut::*;
 
-const MSHR: usize = 3;
 const LSU_IDX_DEFAULT: u8 = 0xff;
 const DATAPATH_WIDTH_IN_BYTES: usize = 8; // 8 = config.datapath_width_in_bytes = beatbyte = lsuBankParameters(0).beatbyte for blastoise
 
@@ -89,18 +88,15 @@ fn load_elf(fname: &Path) -> anyhow::Result<u64> {
   assert_eq!(header.pt1.class(), header::Class::ThirtyTwo);
 
   for ph in elf_file.program_iter() {
-    match ph {
-      ProgramHeader::Ph32(ph) => {
-        if ph.get_type() == Ok(Type::Load) {
-          let offset = ph.offset as usize;
-          let size = ph.file_size as usize;
-          let addr = ph.virtual_addr as usize;
-
-          let slice = &buffer[offset..offset + size];
-          ld(addr, size, slice.to_vec()).unwrap();
-        }
+    if let ProgramHeader::Ph32(ph) = ph {
+      if ph.get_type() == Ok(Type::Load) {
+        let offset = ph.offset as usize;
+        let size = ph.file_size as usize;
+        let addr = ph.virtual_addr as usize;
+
+        let slice = &buffer[offset..offset + size];
+        ld(addr, size, slice.to_vec()).unwrap();
       }
-      _ => (),
     }
   }
 
@@ -134,22 +130,21 @@ pub fn add_rtl_write(se: &mut SpikeEvent, vrf_write: VrfWriteEvent, record_idx_b
 
       if let Some(record) = record_iter {
         assert_eq!(
-          (record.byte as u8),
-          (written_byte as u8),
+          record.byte,
+          written_byte,
           "{j}th byte incorrect ({:02X} != {written_byte:02X}) for vrf \
 						write (lane={}, vd={}, offset={}, mask={:04b}) \
-						[vrf_idx={}] (lsu_idx={}, {})",
+						[vrf_idx={}] (lsu_idx={}, disasm: {}, pc: {:#x}, bits: {:#x})",
           record.byte,
           vrf_write.idx,
           vrf_write.vd,
           vrf_write.offset,
           vrf_write.mask,
           record_idx_base + j,
           se.lsu_idx,
-          format!(
-            "disasm: {}, pc: {:#x}, bits: {:#x}",
-            se.disasm, se.pc, se.inst_bits
-          )
+          se.disasm,
+          se.pc,
+          se.inst_bits
         );
         record.executed = true;
       }
@@ -159,16 +154,11 @@ pub fn add_rtl_write(se: &mut SpikeEvent, vrf_write: VrfWriteEvent, record_idx_b
 
 #[derive(Debug, Clone)]
 pub struct TLReqRecord {
-  data: Vec<u8>,
   cycle: usize,
   size_by_byte: usize,
   addr: u32,
-  source: u16,
 
   muxin_read_required: bool,
-  muxin_read_sent: bool,
-
-  se: SpikeEvent,
 
   // For writes, as soon as the transaction is sent to the controller, the request is resolved, so we don't have to track the number
   //   of bytes that have been processed by the memory controller
@@ -189,25 +179,12 @@ pub struct TLReqRecord {
 }
 
 impl TLReqRecord {
-  pub fn new(
-    se: &SpikeEvent,
-    cycle: usize,
-    data: Vec<u8>,
-    size_by_byte: usize,
-    addr: u32,
-    source: u16,
-    op: Opcode,
-    burst_size: usize,
-  ) -> Self {
+  pub fn new(cycle: usize, size_by_byte: usize, addr: u32, op: Opcode, burst_size: usize) -> Self {
     TLReqRecord {
-      data,
       cycle,
       size_by_byte,
       addr,
-      source,
       muxin_read_required: op == Opcode::PutFullData && size_by_byte < burst_size,
-      muxin_read_sent: false,
-      se: se.clone(),
       bytes_received: 0,
       bytes_committed: 0,
       bytes_processed: 0,
@@ -237,9 +214,9 @@ impl TLReqRecord {
       return Ok(false);
     }
     if self.op == Opcode::PutFullData {
-      return Ok(self.bytes_returned > 0);
+      Ok(self.bytes_returned > 0)
     } else {
-      return Ok(self.bytes_returned >= self.size_by_byte);
+      Ok(self.bytes_returned >= self.size_by_byte)
     }
   }
 }
@@ -513,10 +490,7 @@ impl SpikeHandle {
     if let Some(addr) = self.tl_req_waiting_ready[idx] {
       let req_record = self.tl_req_record_of_bank[idx]
         .get_mut(&addr)
-        .expect(&format!(
-          "cannot find current request with addr {:08X}",
-          addr
-        ));
+        .unwrap_or_else(|| panic!("cannot find current request with addr {addr:08X}"));
 
       req_record
         .commit_tl_respones(DATAPATH_WIDTH_IN_BYTES)
@@ -544,7 +518,7 @@ impl SpikeHandle {
     let idx = peek_tl.idx as usize;
     let tl_data = peek_tl.data;
     let mask = peek_tl.mask;
-    let cycle = peek_tl.cycle as usize;
+    let cycle = peek_tl.cycle;
     let size = peek_tl.size;
     let source = peek_tl.source;
     let base_addr = peek_tl.addr;
@@ -557,17 +531,16 @@ impl SpikeHandle {
       match peek_tl.opcode {
         Opcode::Get => {
           let mut actual_data = vec![0u8; size];
-          for offset in 0..size {
+          for (offset, actual) in actual_data.iter_mut().enumerate().take(size) {
             let addr = base_addr + offset as u32;
             match se.mem_access_record.all_reads.get_mut(&addr) {
               Some(mem_read) => {
-                actual_data[offset] = mem_read.reads[mem_read.num_completed_reads].val;
+                *actual = mem_read.reads[mem_read.num_completed_reads].val;
                 mem_read.num_completed_reads += 1;
               }
               None => {
-                // TODO: check if the cache line should be accessed
                 warn!("[{cycle}] ReceiveTLReq addr: {addr:08X} insn: {} send falsy data 0xDE for accessing unexpected memory", format!("{:x}", se.inst_bits));
-                actual_data[offset as usize] = 0xDE; // falsy data
+                *actual = 0xDE; // falsy data
               }
             }
           }
@@ -579,16 +552,7 @@ impl SpikeHandle {
 
           self.tl_req_record_of_bank[idx].insert(
             cycle,
-            TLReqRecord::new(
-              se,
-              cycle,
-              actual_data,
-              size,
-              base_addr,
-              source,
-              Opcode::Get,
-              1,
-            ),
+            TLReqRecord::new(cycle, size, base_addr, Opcode::Get, 1),
           );
 
           self.tl_req_record_of_bank[idx]
@@ -622,16 +586,7 @@ impl SpikeHandle {
           if cur_record.is_none() {
             // 1 is dummy value, won't be effective whatsoever. 1 is to ensure that no sub-line write is possible
             // here we do not use dramsim3.
-            let record = TLReqRecord::new(
-              se,
-              cycle,
-              vec![0; size],
-              size,
-              base_addr,
-              source,
-              Opcode::PutFullData,
-              1,
-            );
+            let record = TLReqRecord::new(cycle, size, base_addr, Opcode::PutFullData, 1);
             self.tl_req_record_of_bank[idx].insert(cycle, record);
 
             // record moved into self.tl_req_record_of_bank, so we should get it from there
@@ -658,14 +613,14 @@ impl SpikeHandle {
             if (mask >> byte_lane_idx) & 1 != 0 {
               let byte_addr =
                 base_addr + cur_record.as_ref().unwrap().bytes_received as u32 + offset as u32;
-              let tl_data_byte = (tl_data >> 8 * byte_lane_idx) as u8;
+              let tl_data_byte = (tl_data >> (8 * byte_lane_idx)) as u8;
               let mem_write = se
                 .mem_access_record
                 .all_writes
                 .get_mut(&byte_addr)
-                .expect(&format!(
-                  "[{cycle}] cannot find mem write of byte_addr {byte_addr:08x}"
-                ));
+                .unwrap_or_else(|| {
+                  panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:08x}")
+                });
               assert!(
                 mem_write.num_completed_writes < mem_write.writes.len(),
                 "[{cycle}] written size:{} should be smaller than completed writes:{}",

difftest/t1-simulator/src/difftest/spike/libspike_interfaces.rs

@@ -15,7 +15,7 @@ impl Spike {
   }
 
   pub fn get_proc(&self) -> Processor {
-    let processor = unsafe { spike_get_proc(self.spike as *mut ()) };
+    let processor = unsafe { spike_get_proc(self.spike) };
     Processor { processor }
   }
 }