[rtl] Do not allow execution units to return out of order.

chipsalliance · Jun 4, 2024 · a5eefe3 · a5eefe3
1 parent 925a95d
commit a5eefe3
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Showing 2 changed files with 18 additions and 3 deletions.
diff --git a/t1/src/laneStage/LaneExecutionBridge.scala b/t1/src/laneStage/LaneExecutionBridge.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.experimental.hierarchy.{instantiable, public}
 import chisel3.util._
 import chisel3.util.experimental.decode.DecodeBundle
-import org.chipsalliance.t1.rtl.{CSRInterface, ExecutionUnitRecord, LaneParameter, SlotRequestToVFU, VFUResponseToSlot, cutUInt}
+import org.chipsalliance.t1.rtl.{CSRInterface, ExecutionUnitRecord, LaneParameter, SlotRequestToVFU, VFUResponseToSlot, cutUInt, getExecuteUnitTag}
 import org.chipsalliance.t1.rtl.decoder.Decoder
 
 class LaneExecuteRequest(parameter: LaneParameter, isLastSlot: Boolean) extends Bundle {
@@ -137,7 +137,6 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
       executionRecord.executeIndex := firstGroupNotExecute || !enqueue.fire
     }
   }
-  enqueue.ready := !executionRecordValid || recordDequeueReady
 
   when(enqueue.fire) {
     executionRecord.crossReadVS2 := enqueue.bits.decodeResult(Decoder.crossRead) && !enqueue.bits.decodeResult(Decoder.vwmacc)
@@ -552,4 +551,8 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
     (!recordQueue.io.deq.bits.sSendResponse.get && queue.io.enq.fire) ||
       (enqueue.fire && enqueue.bits.groupCounter === 0.U)
   )
+  val executionTypeInRecord: UInt = getExecuteUnitTag(parameter)(executionRecord.decodeResult)
+  val enqType: UInt = getExecuteUnitTag(parameter)(enqueue.bits.decodeResult)
+  val typeCheck: Bool = (executionTypeInRecord === enqType) || !(executionRecordValid || recordQueue.io.deq.valid)
+  enqueue.ready := (!executionRecordValid || recordDequeueReady) && typeCheck
 }
diff --git a/t1/src/package.scala b/t1/src/package.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.experimental.hierarchy.{Instance, Instantiate}
 import chisel3.util._
 import chisel3.util.experimental.decode.DecodeBundle
-import org.chipsalliance.t1.rtl.decoder.TableGenerator
+import org.chipsalliance.t1.rtl.decoder.{Decoder, TableGenerator}
 import org.chipsalliance.t1.rtl.lane.Distributor
 import tilelink.{TLBundleParameter, TLChannelD}
 
@@ -334,4 +334,16 @@ package object rtl {
     sink.bits := source.bits
     source.ready := sink.ready && enable
   }
+
+  def getExecuteUnitTag(parameter: LaneParameter)(inputDecode: DecodeBundle): UInt = {
+    val executeList: Seq[Bool] = Seq(
+      inputDecode(Decoder.logic),
+      inputDecode(Decoder.adder),
+      inputDecode(Decoder.shift),
+      inputDecode(Decoder.multiplier),
+      inputDecode(Decoder.divider),
+      inputDecode(Decoder.other),
+    ) ++ Option.when(parameter.fpuEnable)(inputDecode(Decoder.float))
+    VecInit(executeList).asUInt
+  }
 }