[rocketv] only FIOM is writable currently, successuflly elaborate roc…

…ketv with msu priv
chipsalliance · Aug 8, 2024 · a56ebd2 · a56ebd2
1 parent 11cb691
commit a56ebd2
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Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/rocketv/configs/meowth.json → rocketv/configs/Greninja.json b/rocketv/configs/meowth.json → rocketv/configs/Greninja.json
@@ -3,7 +3,7 @@
     "useAsyncReset": false,
     "clockGate": true,
     "instructionSets": ["rv32_i"],
-    "priv": "m",
+    "priv": "msu",
     "hartIdLen": 4,
     "useBPWatch": false,
     "mcontextWidth": 0,

diff --git a/rocketv/src/CSR.scala b/rocketv/src/CSR.scala
@@ -368,7 +368,7 @@ class CSR(val parameter: CSRParameter)
     case (32, 2)                     => 1
     case (64, x) if x >= 3 && x <= 6 => x + 5
   }
-  def write(fiom: Envcfg, wdata: UInt) {
+  def write(fiom: Bool, wdata: UInt) {
     val new_envcfg = wdata.asTypeOf(new Envcfg)
     fiom := new_envcfg.fiom // only FIOM is writable currently
   }
@@ -1528,7 +1528,7 @@ class CSR(val parameter: CSRParameter)
       when(decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata }
       when(decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata }
       when(decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata }
-      when(decoded_addr(CSRs.senvcfg)) { write(reg_senvcfg, wdata) }
+      when(decoded_addr(CSRs.senvcfg)) { write(reg_senvcfg.fiom, wdata) }
     }
 
     if (usingHypervisor) {
@@ -1603,11 +1603,11 @@ class CSR(val parameter: CSRParameter)
       when(decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata }
       when(decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask }
       when(decoded_addr(CSRs.vstval)) { reg_vstval := wdata }
-      when(decoded_addr(CSRs.henvcfg)) { write(reg_henvcfg, wdata) }
+      when(decoded_addr(CSRs.henvcfg)) { write(reg_henvcfg.fiom, wdata) }
     }
     if (usingUser) {
       when(decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata }
-      when(decoded_addr(CSRs.menvcfg)) { write(reg_menvcfg, wdata) }
+      when(decoded_addr(CSRs.menvcfg)) { write(reg_menvcfg.fiom, wdata) }
     }
     if (nBreakpoints > 0) {
       when(decoded_addr(CSRs.tselect)) { reg_tselect := wdata }