[rtl] use piped decode result when connect vfu.

chipsalliance · May 30, 2024 · a50ead5 · a50ead5
1 parent 9a7ed06
commit a50ead5
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Showing 3 changed files with 21 additions and 10 deletions.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -466,6 +466,12 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   /** request from slot to vfu. */
   val requestVec: Vec[SlotRequestToVFU] = Wire(Vec(parameter.chainingSize, new SlotRequestToVFU(parameter)))
 
+  /** decode message for [[requestVec]]. */
+  val executeDecodeVec: Vec[DecodeBundle] = Wire(Vec(parameter.chainingSize, Decoder.bundle(parameter.fpuEnable)))
+
+  /** decode message for [[responseVec]]. */
+  val responseDecodeVec: Vec[DecodeBundle] = Wire(Vec(parameter.chainingSize, Decoder.bundle(parameter.fpuEnable)))
+
   /** response from vfu to slot. */
   val responseVec: Vec[ValidIO[VFUResponseToSlot]] = Wire(Vec(parameter.chainingSize, Valid(new VFUResponseToSlot(parameter))))
 
@@ -726,6 +732,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
       // executionUnit <> vfu
       requestVec(index) := executionUnit.vfuRequest.bits
+      executeDecodeVec(index) := executionUnit.executeDecode
+      responseDecodeVec(index) := executionUnit.responseDecode
       executeEnqueueValid(index) := executionUnit.vfuRequest.valid
       executionUnit.vfuRequest.ready := executeEnqueueFire(index)
       executionUnit.dataResponse := responseVec(index)
@@ -820,17 +828,12 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     assert(queue.io.enq.ready || !port.enq.valid)
     port.enqRelease := queue.io.deq.fire
   }
-  // convert data types
-
-
-  // VFU
-  // TODO: reuse logic, adder, multiplier datapath
-  val decodeResultVec: Seq[DecodeBundle] = slotControl.map(_.laneRequest.decodeResult)
 
   val vfus: Seq[Instance[VFUModule]] = instantiateVFU(parameter.vfuInstantiateParameter)(
     requestVec,
     executeEnqueueValid,
-    decodeResultVec,
+    executeDecodeVec,
+    responseDecodeVec,
     executeEnqueueFire,
     responseVec,
     executeOccupied,

diff --git a/t1/src/laneStage/LaneExecutionBridge.scala b/t1/src/laneStage/LaneExecutionBridge.scala
@@ -67,6 +67,11 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
   @public
   val selfCompleted: Bool = IO(Input(Bool()))
 
+  @public
+  val executeDecode: DecodeBundle = IO(Output(Decoder.bundle(parameter.fpuEnable)))
+  @public
+  val responseDecode: DecodeBundle = IO(Output(Decoder.bundle(parameter.fpuEnable)))
+
   val executionRecord: ExecutionUnitRecord = RegInit(0.U.asTypeOf(new ExecutionUnitRecord(parameter)(isLastSlot)))
   val executionRecordValid = RegInit(false.B)
 
@@ -293,6 +298,7 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
 
   // from float csr
   vfuRequest.bits.roundingMode.foreach(_ := executionRecord.csr.vxrm)
+  executeDecode := executionRecord.decodeResult
 
   vfuRequest.valid := (if (isLastSlot) {
     (executionRecordValid || sendFoldReduce.get) && (responseFinish || !executionRecord.decodeResult(Decoder.red))
@@ -534,6 +540,7 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
   queue.io.enq.bits.ffoSuccess.foreach(_ := dataResponse.bits.ffoSuccess)
   queue.io.enq.bits.fpReduceValid.foreach(_ := !waitFirstValidFire.get)
   recordQueue.io.deq.ready := dataResponse.valid || (recordNotExecute && queue.io.enq.ready)
+  responseDecode := recordQueue.io.deq.bits.decodeResult
   queue.io.enq.valid :=
     (recordQueue.io.deq.valid &&
       ((dataResponse.valid && reduceReady &&

diff --git a/t1/src/package.scala b/t1/src/package.scala
@@ -183,7 +183,8 @@ package object rtl {
   def instantiateVFU(parameter: VFUInstantiateParameter)(
     requestVec: Vec[SlotRequestToVFU],
     requestValid: Vec[Bool],
-    decodeResult: Seq[DecodeBundle],
+    requestDecode: Seq[DecodeBundle],
+    responseDecode: Seq[DecodeBundle],
     executeEnqueueFire: Vec[Bool],
     responseVec: Vec[ValidIO[VFUResponseToSlot]],
     executeOccupied: Vec[Bool],
@@ -200,7 +201,7 @@ package object rtl {
       val requestFire = request.elements.map { case (name: String, reqForVfu: DecoupledIO[SlotRequestToVFU]) =>
         // 检测类型
         val requestParameter: VFUParameter = request.parameterMap(name)
-        val typeCheck = decodeResult(slotIndex)(requestParameter.decodeField)
+        val typeCheck = requestDecode(slotIndex)(requestParameter.decodeField)
         // 连接 valid
         reqForVfu.valid := requestValid(slotIndex) && typeCheck
 
@@ -296,7 +297,7 @@ package object rtl {
       // 筛选 response
       val responseFilter: Seq[(Bool, ValidIO[VFUResponseToSlot])] = vfuResponse.zip(parameter.genVec).filter(_._2._2.contains(slotIndex)).map {
         case (resp, (gen, _)) =>
-          (decodeResult(slotIndex)(gen.parameter.decodeField), resp)
+          (responseDecode(slotIndex)(gen.parameter.decodeField), resp)
       }
       val selectResponse: ValidIO[VFUResponseToSlot] = Mux1H(
         responseFilter.map(_._1),