Skip to content

Commit

Permalink
[emulator] rewrite Lane probes to latest perf model
Browse files Browse the repository at this point in the history 
Signed-off-by: Avimitin <[email protected]>
  • Loading branch information
@Avimitin
Avimitin committed Oct 31, 2023
1 parent fca5ddc commit 9e43c0f
Show file tree
Hide file tree
Showing 4 changed files with 55 additions and 415 deletions.
63 changes: 9 additions & 54 deletions elaborator/src/PerfMonitor.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,19 +9,6 @@ abstract class PerfMonitor extends DPIModule {
override val trigger: String = s"always @(posedge ${clock.name})";
}

trait IndexedPerfMonitor extends PerfMonitor {
val index = dpiIn("index", Input(UInt(32.W)))
}

trait ValidMonitor extends PerfMonitor {
val isValid = dpiIn("isValid", Input(Bool()))
}

trait ReadyMonitor extends PerfMonitor {
val isReady = dpiIn("isReady", Input(Bool()))
}


/**
* Monitor signals in [[v.LoadUnit]] [[v.StoreUnit]]
*/
Expand Down Expand Up @@ -123,46 +110,14 @@ class OtherUnitMonitor extends PerfMonitor {
}
// End of SimpleAccessUnit monitors definition

class LaneReadBusPortMonitor extends IndexedPerfMonitor {
val readBusPortEnqReady = dpiIn("readBusPortEnqReady", Input(Bool()))
val readBusPortEnqValid = dpiIn("readBusPortEnqValid", Input(Bool()))
val readBusPortDeqReady = dpiIn("readBusPortDeqReady", Input(Bool()))
val readBusPortDeqValid = dpiIn("readBusPortDeqValid", Input(Bool()))
}

class LaneWriteBusPortMonitor extends IndexedPerfMonitor {
val writeBusPortEnqReady = dpiIn("writeBusPortEnqReady", Input(Bool()))
val writeBusPortEnqValid = dpiIn("writeBusPortEnqValid", Input(Bool()))
val writeBusPortDeqReady = dpiIn("writeBusPortDeqReady", Input(Bool()))
val writeBusPortDeqValid = dpiIn("writeBusPortDeqValid", Input(Bool()))
}

class LaneRequestMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneResponseMonitor extends IndexedPerfMonitor with ValidMonitor {
val laneResponseFeedbackValid = dpiIn("laneResponseFeedbackValid", Input(Bool()))
}

class LaneVrfReadMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneVrfWriteMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneStatusMonitor extends IndexedPerfMonitor {
val v0UpdateValid = dpiIn("v0UpdateValid", Input(Bool()))
val writeReadyForLsu = dpiIn("writeReadyForLsu", Input(Bool()))
val vrfReadyToStore = dpiIn("vrfReadyToStore", Input(Bool()))
}

class LaneWriteQueueMonitor extends IndexedPerfMonitor with ValidMonitor

class LaneReadBusDequeueMonitor extends IndexedPerfMonitor with ValidMonitor

class CrossLaneMonitor extends IndexedPerfMonitor {
val readValid = dpiIn("crossLaneReadValid", Input(Bool()))
val writeValid = dpiIn("crossLaneWriteValid", Input(Bool()))
case class LaneParam(slot: Int)
class LaneMonitor(param: LaneParam) extends PerfMonitor {
val index = dpiIn("index", Input(UInt(32.W)))
val laneRequestValid = dpiIn("laneRequestValid", Input(Bool()))
val laneRequestReady = dpiIn("laneRequestReady", Input(Bool()))
val lastSlotOccupied = dpiIn("lastSlotOccupied", Input(Bool()))
val vrfInstructionWriteReportReady = dpiIn("vrfInstructionWriteReportReady", Input(Bool()))
val slotOccupied = dpiIn("slotOccupied", Seq.fill(param.slot)(Input(Bool())))
val instructionFinished = dpiIn("instructionFinished", Input(UInt(32.W)))
}

class LaneReadBusDataMonitor extends IndexedPerfMonitor with ValidMonitor

class LaneWriteBusDataMonitor extends IndexedPerfMonitor with ValidMonitor
// End of Lane monitor
108 changes: 11 additions & 97 deletions elaborator/src/TestBench.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -144,102 +144,16 @@ class TestBench(generator: SerializableModuleGenerator[V, VParameter]) extends R
// End of [[v.SimpleAccessUnit]] related probe connection

dut.laneVec.zipWithIndex.foreach({ case (lane, i) =>
{
val monitor = Module(new LaneReadBusPortMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.readBusPortEnqReady.ref := read(bore(lane.readBusPortEnqReadyProbe))
monitor.readBusPortEnqValid.ref := read(bore(lane.readBusPortEnqValidProbe))
monitor.readBusPortDeqReady.ref := read(bore(lane.readBusPortDeqReadyProbe))
monitor.readBusPortDeqValid.ref := read(bore(lane.readBusPortDeqValidProbe))
}
{
val monitor = Module(new LaneWriteBusPortMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.writeBusPortDeqReady.ref := read(bore(lane.writeBusPortDeqReadyProbe))
monitor.writeBusPortDeqValid.ref := read(bore(lane.writeBusPortDeqValidProbe))
monitor.writeBusPortEnqReady.ref := read(bore(lane.writeBusPortEnqReadyProbe))
monitor.writeBusPortEnqValid.ref := read(bore(lane.writeBusPortEnqValidProbe))
}
{
val monitor = Module(new LaneRequestMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.isReady.ref := read(bore(lane.laneRequestReadyProbe))
monitor.isValid.ref := read(bore(lane.laneRequestValidProbe))
}
{
val monitor = Module(new LaneResponseMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.isValid.ref := read(bore(lane.laneResponseValidProbe))
monitor.laneResponseFeedbackValid.ref := read(bore(lane.laneResponseFeedbackValidProbe))
}
{
val monitor = Module(new LaneVrfReadMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.isValid.ref := read(bore(lane.vrfReadAddressChannelValidProbe))
monitor.isReady.ref := read(bore(lane.vrfReadAddressChannelReadyProbe))
}
{
val monitor = Module(new LaneVrfWriteMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.isValid.ref := read(bore(lane.vrfWriteChannelValidProbe))
monitor.isReady.ref := read(bore(lane.vrfWriteChannelReadyProbe))
}
{
val monitor = Module(new LaneStatusMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.v0UpdateValid.ref := read(bore(lane.v0UpdateValidProbe))
monitor.writeReadyForLsu.ref := read(bore(lane.writeReadyForLsuProbe))
monitor.vrfReadyToStore.ref := read(bore(lane.vrfReadyToStoreProbe))
}
{
val monitor = Module(new LaneWriteQueueMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.isValid.ref := read(bore(lane.writeQueueValidProbe))
}
{
val monitor = Module(new LaneReadBusDequeueMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.isValid.ref := read(bore(lane.readBusDequeueValidProbe))
}
{
val monitor = Module(new CrossLaneMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.readValid.ref := read(bore(lane.crossLaneReadValidProbe))
monitor.writeValid.ref := read(bore(lane.crossLaneWriteValidProbe))
}
{
val monitor = Module(new LaneReadBusDataMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.isValid.ref := read(bore(lane.readBusDataReqValidProbe))
}
{
val monitor = Module(new LaneWriteBusDataMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.isValid.ref := read(bore(lane.writeBusDataReqValidProbe))
}
val laneMonitor = Module(new LaneMonitor(LaneParam(generator.parameter.chainingSize)))
laneMonitor.clock.ref := clock.asBool
laneMonitor.index.ref := i.U
laneMonitor.laneRequestReady.ref := read(bore(lane.laneRequestReadyProbe))
laneMonitor.laneRequestValid.ref := read(bore(lane.laneRequestValidProbe))
laneMonitor.lastSlotOccupied.ref := read(bore(lane.lastSlotOccupiedProbe))
laneMonitor.vrfInstructionWriteReportReady.ref := read(bore(lane.vrfInstructionWriteReportReadyProbe))
laneMonitor.slotOccupied.zipWithIndex.foreach { case(dpi, index) =>
dpi.ref := read(bore(lane.slotOccupiedProbe(index)))
}
laneMonitor.instructionFinished.ref := read(bore(lane.instructionFinishedProbe))
})
}
195 changes: 25 additions & 170 deletions emulator/src/dpi.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -362,183 +362,38 @@ void other_unit_monitor(svLogic lsuRequestIsValid, svLogic s0EnqueueValid,
.with("s0_fire", (bool)s0Fire)
.with("s1_fire", (bool)s1Fire)
.with("s2_fire", (bool)s2Fire)
.with("tl_port_a", json {
{ "valid", (bool)tlPortAIsValid },
{ "ready", (bool)tlPortAIsReady }
})
.with("tl_port_a", json{{"valid", (bool)tlPortAIsValid},
{"ready", (bool)tlPortAIsReady}})
.with("s1_valid", (bool)s1Valid)
.with("source_free", (bool)sourceFree)
.with("tl_port_d", json {
{ "valid", (bool)tlPortDIsValid },
{ "ready", (bool)tlPortDIsReady }
})
.with("vrf_write_port", json {
{ "valid", (bool)VrfWritePortIsValid },
{ "ready", (bool)VrfWritePortIsReady }
})
.info();
})
}

[[maybe_unused]] void lane_read_bus_port_monitor(
const svBitVecVal *index, const svBit read_bus_port_enq_ready,
const svBit read_bus_port_enq_valid, const svBit read_bus_port_deq_ready,
const svBit read_bus_port_deq_valid) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("read_bus_port",
json{{"enq",
{{"is_ready", (bool)read_bus_port_enq_ready},
{"is_valid", (bool)read_bus_port_enq_valid}}},
{"deq",
{{"is_ready", (bool)read_bus_port_deq_ready},
{"is_valid", (bool)read_bus_port_deq_valid}}}})
.info();
})
}

[[maybe_unused]] void lane_write_bus_port_monitor(
const svBitVecVal *index, const svBit write_bus_port_enq_ready,
const svBit write_bus_port_enq_valid, const svBit write_bus_port_deq_ready,
const svBit write_bus_port_deq_valid) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("write_bus_port",
json{{"enq",
{{"is_ready", (bool)write_bus_port_enq_ready},
{"is_valid", (bool)write_bus_port_enq_valid}}},
{"deq",
{{"is_ready", (bool)write_bus_port_deq_ready},
{"is_valid", (bool)write_bus_port_deq_valid}}}})
.with("tl_port_d", json{{"valid", (bool)tlPortDIsValid},
{"ready", (bool)tlPortDIsReady}})
.with("vrf_write_port", json{{"valid", (bool)VrfWritePortIsValid},
{"ready", (bool)VrfWritePortIsReady}})
.info();
})
}

[[maybe_unused]] void lane_request_monitor(const svBitVecVal *index,
const svBit lane_request_valid,
const svBit lane_request_ready) {
void lane_monitor(const svBitVecVal *index, svLogic laneRequestValid,
svLogic laneRequestReady, svLogic lastSlotOccupied,
svLogic vrfInstructionWriteReportReady, svLogic slotOccupied0,
svLogic slotOccupied1, svLogic slotOccupied2,
svLogic slotOccupied3,
const svBitVecVal *instructionFinished) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("lane_request", json{{"is_valid", (bool)lane_request_valid},
{"is_ready", (bool)lane_request_ready}})
.info();
})
}

[[maybe_unused]] void
lane_response_monitor(const svBitVecVal *index, const svBit lane_response_valid,
const svBit lane_response_feedback_valid) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("lane_response", json{{"is_valid", (bool)lane_response_valid}})
.with("lane_response_feedback",
json{{"is_valid", (bool)lane_response_feedback_valid}})
.info();
})
}

[[maybe_unused]] void lane_vrf_read_monitor(const svBitVecVal *index,
const svBit is_valid,
const svBit is_ready) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("vrf_read_address_channel",
json{
{"is_valid", (bool)is_valid},
{"is_ready", (bool)is_ready},
})
.info();
})
}

[[maybe_unused]] void lane_vrf_write_monitor(const svBitVecVal *index,
const svBit is_valid,
const svBit is_ready) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("vrf_write_channel",
json{
{"is_valid", (bool)is_valid},
{"is_ready", (bool)is_ready},
})
.info();
})
}

[[maybe_unused]] void lane_status_monitor(const svBitVecVal *index,
const svBit v0_update_valid,
const svBit write_ready_for_lsu,
const svBit vrf_ready_to_store) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("v0_update_valid", (bool)v0_update_valid)
.with("write_ready_for_lsu", (bool)write_ready_for_lsu)
.with("vrf_ready_to_store", (bool)vrf_ready_to_store)
.info();
})
}

[[maybe_unused]] void lane_write_queue_monitor(const svBitVecVal *index,
const svBit write_queue_valid) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("write_queue_valid", (bool)write_queue_valid)
.info();
})
}

[[maybe_unused]] void
lane_read_bus_dequeue_monitor(const svBitVecVal *index,
const svBit read_bus_dequeue_valid) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("read_bus_dequeue_valid", (bool)read_bus_dequeue_valid)
.info();
})
}

[[maybe_unused]] void cross_lane_monitor(const svBitVecVal *index,
const svBit cross_lane_read_valid,
const svBit cross_lane_write_valid) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("cross_lane",
json{
{"read_valid", (bool)cross_lane_read_valid},
{"write_valid", (bool)cross_lane_write_valid},
})
.info();
})
}

[[maybe_unused]] void
lane_read_bus_data_monitor(const svBitVecVal *index,
const svBit read_bus_data_req_valid) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("read_bus_data_req_valid", (bool)read_bus_data_req_valid)
.info();
})
}

[[maybe_unused]] void
lane_write_bus_data_monitor(const svBitVecVal *index,
const svBit write_bus_data_req_valid) {
TRY({
Log("LaneMonitor")
.with("lane_index", (int)(*index))
.with("write_bus_data_req_valid", (bool)write_bus_data_req_valid)
Log("Lane")
.with("index", (int)(*index))
.with("lane_request", json{{"valid", (bool)laneRequestValid},
{"ready", (bool)laneRequestReady}})
.with("last_slot_occpied", (bool)lastSlotOccupied)
.with("vrf_instruction_write_report_ready", (bool)vrfInstructionWriteReportReady)
.with("slot_occpied", std::vector{
(bool)slotOccupied0,
(bool)slotOccupied1,
(bool)slotOccupied2,
(bool)slotOccupied3,
})
.with("instruction_finished", (int)(*instructionFinished))
.info();
})
}
Expand Down
Loading

0 comments on commit 9e43c0f

Please sign in to comment.