[rtl] Handle the boundary for mask source.

chipsalliance · Jan 25, 2024 · 9ae8790 · 9ae8790
1 parent 833b364
commit 9ae8790
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -913,7 +913,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   val maskeDataGroup = (vlHead ## vlBody) - !dataPathMisaligned
   val lastLaneIndexForMaskLogic: UInt = maskeDataGroup(parameter.laneNumberBits - 1, 0)
   val isLastLaneForMaskLogic: Bool = lastLaneIndexForMaskLogic === laneIndex
-  val lastGroupCountForMaskLogic: UInt = (maskeDataGroup >> parameter.laneNumberBits).asUInt
+  val lastGroupCountForMaskLogic: UInt = (maskeDataGroup >> parameter.laneNumberBits).asUInt -
+    ((vlBody.orR || dataPathMisaligned) && (laneIndex > lastLaneIndexForMaskLogic))
   val misalignedForOther: Bool = Mux1H(
     requestVSew1H(1, 0),
     Seq(