[doc] refactor and add all attributes

t1/src/decoder/Decoder.scala

@@ -187,34 +187,35 @@ object Decoder {
         Op(tpe, funct6, tpeOp2, funct3, insn.name, special, notLSU=true, vd, opcode)
       }
       // case of LSU instructions: `opcodeLoadF` and `opcodeStoreF`
-      ++ Seq("1", "0").map(fun6End =>
+      ++ instructions.filter(_.encoding.toString.substring(32-6-1, 32-0) == opcodeLoadF).map{ insn =>
+        val funct6 = insn.encoding.toString.substring(32-31-1, 32-26)
         Op(
           "I",               // tpe
-          "?????" + fun6End,
+          funct6,
           "?",               // tpeOp2
           "???",             // funct3
-          "lsu",
+          insn.name,
           None,
           notLSU = false,
           "?????",           // vd
           opcodeLoadF
         )
-      )
-      ++ Seq("1", "0").map(fun6End =>
+      }
+      ++ instructions.filter(_.encoding.toString.substring(32-6-1, 32-0) == opcodeStoreF).map{ insn =>
+        val funct6 = insn.encoding.toString.substring(32-31-1, 32-26)
         Op(
           "I",               // tpe
-          "?????" + fun6End,
+          funct6,
           "?",               // tpeOp2
           "???",             // funct3
-          "lsu",
+          insn.name,
           None,
           notLSU = false,
           "?????",           // vd
           opcodeStoreF
         )
-      )
+      }
     ).toArray
-
     expandedOps.filter(_.tpe != "F" || fpuEnable)
   }
 

t1/src/decoder/T1DecodePattern.scala

@@ -11,7 +11,7 @@ import chisel3.util.BitPat
 import chisel3.util.experimental.decode.DecodePattern
 import org.chipsalliance.rvdecoderdb.Instruction
 import org.chipsalliance.t1.rtl.T1Parameter
-import org.chipsalliance.t1.rtl.decoder.attribute.isVector
+import org.chipsalliance.t1.rtl.decoder.attribute._
 
 @instantiable
 class T1DecodeAttributeOM extends Class {
@@ -57,6 +57,60 @@ case class T1DecodePattern(instruction: Instruction, t1Parameter: T1Parameter) e
 
   // use the attribute w/ [[isVector.value]]
   def isVector: isVector = attribute.isVector(this)
+  def isAdder: isAdder = attribute.isAdder(this)
+  def isAverage: isAverage = attribute.isAverage(this)
+  def isCompress: isCompress = attribute.isCompress(this)
+  def isCrossread: isCrossread = attribute.isCrossread(this)
+  def isCrosswrite: isCrosswrite = attribute.isCrosswrite(this)
+  def isDivider: isDivider = attribute.isDivider(this)
+  def isDontneedexecuteinlane: isDontneedexecuteinlane = attribute.isDontneedexecuteinlane(this)
+  def isExtend: isExtend = attribute.isExtend(this)
+  def isFcompare: isFcompare = attribute.isFcompare(this)
+  def isFfo: isFfo = attribute.isFfo(this)
+  def isFirstwiden: isFirstwiden = attribute.isFirstwiden(this)
+  def isFloatmul: isFloatmul = attribute.isFloatmul(this)
+  def isFloat: isFloat = attribute.isFloat(this)
+  def isFloattype: isFloattype = attribute.isFloattype(this)
+  def isFma: isFma = attribute.isFma(this)
+  def isFother: isFother = attribute.isFother(this)
+  def isGather16: isGather16 = attribute.isGather16(this)
+  def isGather: isGather = attribute.isGather(this)
+  def isId: isId = attribute.isId(this)
+  def isIndextype: isIndextype = attribute.isIndextype(this)
+  def isIota: isIota = attribute.isIota(this)
+  def isItype: isItype = attribute.isItype(this)
+  def isLogic: isLogic = attribute.isLogic(this)
+  def isMa: isMa = attribute.isMa(this)
+  def isMaskdestination: isMaskdestination = attribute.isMaskdestination(this)
+  def isMasklogic: isMasklogic = attribute.isMasklogic(this)
+  def isMasksource: isMasksource = attribute.isMasksource(this)
+  def isMaskunit: isMaskunit = attribute.isMaskunit(this)
+  def isMulticycle: isMulticycle = attribute.isMulticycle(this)
+  def isMultiplier: isMultiplier = attribute.isMultiplier(this)
+  def isMv: isMv = attribute.isMv(this)
+  def isNarrow: isNarrow = attribute.isNarrow(this)
+  def isNr: isNr = attribute.isNr(this)
+  def isOrderreduce: isOrderreduce = attribute.isOrderreduce(this)
+  def isOther: isOther = attribute.isOther(this)
+  def isPopcount: isPopcount = attribute.isPopcount(this)
+  def isReadonly: isReadonly = attribute.isReadonly(this)
+  def isRed: isRed = attribute.isRed(this)
+  def isReverse: isReverse = attribute.isReverse(this)
+  def isSaturate: isSaturate = attribute.isSaturate(this)
+  def isScheduler: isScheduler = attribute.isScheduler(this)
+  def isShift: isShift = attribute.isShift(this)
+  def isSlid: isSlid = attribute.isSlid(this)
+  def isSpecial: isSpecial = attribute.isSpecial(this)
+  def isSpecialslot: isSpecialslot = attribute.isSpecialslot(this)
+  def isSreadvd: isSreadvd = attribute.isSreadvd(this)
+  def isSwrite: isSwrite = attribute.isSwrite(this)
+  def isTargetrd: isTargetrd = attribute.isTargetrd(this)
+  def isUnorderwrite: isUnorderwrite = attribute.isUnorderwrite(this)
+  def isUnsigned0: isUnsigned0 = attribute.isUnsigned0(this)
+  def isUnsigned1: isUnsigned1 = attribute.isUnsigned1(this)
+  def isVtype: isVtype = attribute.isVtype(this)
+  def isVwmacc: isVwmacc = attribute.isVwmacc(this)
+  def isWidenreduce: isWidenreduce = attribute.isWidenreduce(this)
 
   private def documentation: String = InstructionDocumentation(instruction, t1Parameter).toString
 
@@ -74,6 +128,60 @@ case class T1DecodePattern(instruction: Instruction, t1Parameter: T1Parameter) e
     obj.attributesIn :#= Property(
       Seq(
         isVector,
+        isAdder,
+        isAverage,
+        isCompress,
+        isCrossread,
+        isCrosswrite,
+        isDivider,
+        isDontneedexecuteinlane,
+        isExtend,
+        isFcompare,
+        isFfo,
+        isFirstwiden,
+        isFloatmul,
+        isFloat,
+        isFloattype,
+        isFma,
+        isFother,
+        isGather16,
+        isGather,
+        isId,
+        isIndextype,
+        isIota,
+        isItype,
+        isLogic,
+        isMa,
+        isMaskdestination,
+        isMasklogic,
+        isMasksource,
+        isMaskunit,
+        isMulticycle,
+        isMultiplier,
+        isMv,
+        isNarrow,
+        isNr,
+        isOrderreduce,
+        isOther,
+        isPopcount,
+        isReadonly,
+        isRed,
+        isReverse,
+        isSaturate,
+        isScheduler,
+        isShift,
+        isSlid,
+        isSpecial,
+        isSpecialslot,
+        isSreadvd,
+        isSwrite,
+        isTargetrd,
+        isUnorderwrite,
+        isUnsigned0,
+        isUnsigned1,
+        isVtype,
+        isVwmacc,
+        isWidenreduce,
       ).map(_.om.as(attributeClassTpe))
     )
     obj.getPropertyReference

t1/src/decoder/attribute/isAdder.scala

@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]>
+
+package org.chipsalliance.t1.rtl.decoder.attribute
+
+import org.chipsalliance.t1.rtl.decoder.T1DecodePattern
+
+object isAdder {
+  def apply(t1DecodePattern: T1DecodePattern): isAdder =
+    Seq(
+      y _ -> Y,
+      n _ -> N,
+      dc _ -> DC
+    ).collectFirst {
+      case (fn, tri) if fn(t1DecodePattern) => isAdder(tri)
+    }.get
+
+  def y(t1DecodePattern: T1DecodePattern): Boolean = {
+    val allMatched = Seq(
+      "vaadd.vv",
+      "vaadd.vx",
+      "vaaddu.vv",
+      "vaaddu.vx",
+      "vadc.vim",
+      "vadc.vvm",
+      "vadc.vxm",
+      "vadd.vi",
+      "vadd.vv",
+      "vadd.vx",
+      "vasub.vv",
+      "vasub.vx",
+      "vasubu.vv",
+      "vasubu.vx",
+      "vmadc.vi",
+      "vmadc.vim",
+      "vmadc.vv",
+      "vmadc.vvm",
+      "vmadc.vx",
+      "vmadc.vxm",
+      "vmax.vv",
+      "vmax.vx",
+      "vmaxu.vv",
+      "vmaxu.vx",
+      "vmin.vv",
+      "vmin.vx",
+      "vminu.vv",
+      "vminu.vx",
+      "vmsbc.vv",
+      "vmsbc.vvm",
+      "vmsbc.vx",
+      "vmsbc.vxm",
+      "vmseq.vi",
+      "vmseq.vv",
+      "vmseq.vx",
+      "vmsgt.vi",
+      "vmsgt.vx",
+      "vmsgtu.vi",
+      "vmsgtu.vx",
+      "vmsle.vi",
+      "vmsle.vv",
+      "vmsle.vx",
+      "vmsleu.vi",
+      "vmsleu.vv",
+      "vmsleu.vx",
+      "vmslt.vv",
+      "vmslt.vx",
+      "vmsltu.vv",
+      "vmsltu.vx",
+      "vmsne.vi",
+      "vmsne.vv",
+      "vmsne.vx",
+      "vredmax.vs",
+      "vredmaxu.vs",
+      "vredmin.vs",
+      "vredminu.vs",
+      "vredsum.vs",
+      "vrsub.vi",
+      "vrsub.vx",
+      "vsadd.vi",
+      "vsadd.vv",
+      "vsadd.vx",
+      "vsaddu.vi",
+      "vsaddu.vv",
+      "vsaddu.vx",
+      "vsbc.vvm",
+      "vsbc.vxm",
+      "vssub.vv",
+      "vssub.vx",
+      "vssubu.vv",
+      "vssubu.vx",
+      "vsub.vv",
+      "vsub.vx",
+      "vwadd.vv",
+      "vwadd.vx",
+      "vwadd.wv",
+      "vwadd.wx",
+      "vwaddu.vv",
+      "vwaddu.vx",
+      "vwaddu.wv",
+      "vwaddu.wx",
+      "vwredsum.vs",
+      "vwredsumu.vs",
+      "vwsub.vv",
+      "vwsub.vx",
+      "vwsub.wv",
+      "vwsub.wx",
+      "vwsubu.vv",
+      "vwsubu.vx",
+      "vwsubu.wv",
+      "vwsubu.wx",
+    )
+    allMatched.contains(t1DecodePattern.instruction)
+  }
+  def n(t1DecodePattern: T1DecodePattern): Boolean = {
+    val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i =>
+      !(y(t1DecodePattern) || dc(t1DecodePattern))
+    )
+    allMatched.contains(t1DecodePattern.instruction)
+  }
+
+  def dc(t1DecodePattern: T1DecodePattern): Boolean = false
+}
+
+case class isAdder(value: TriState) extends BooleanDecodeAttribute {
+  override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneAdder]]."
+}

t1/src/decoder/attribute/isAverage.scala

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]>
+
+package org.chipsalliance.t1.rtl.decoder.attribute
+
+import org.chipsalliance.t1.rtl.decoder.T1DecodePattern
+
+object isAverage {
+  def apply(t1DecodePattern: T1DecodePattern): isAverage =
+    Seq(
+      y _ -> Y,
+      n _ -> N,
+      dc _ -> DC
+    ).collectFirst {
+      case (fn, tri) if fn(t1DecodePattern) => isAverage(tri)
+    }.get
+
+  def y(t1DecodePattern: T1DecodePattern): Boolean = {
+    val allMatched = Seq(
+      "vaadd.vv",
+      "vaadd.vx",
+      "vaaddu.vv",
+      "vaaddu.vx",
+      "vasub.vv",
+      "vasub.vx",
+      "vasubu.vv",
+      "vasubu.vx",
+    )
+    allMatched.contains(t1DecodePattern.instruction)
+  }
+  def n(t1DecodePattern: T1DecodePattern): Boolean = {
+    val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i =>
+      !(y(t1DecodePattern) || dc(t1DecodePattern))
+    )
+    allMatched.contains(t1DecodePattern.instruction)
+  }
+
+  def dc(t1DecodePattern: T1DecodePattern): Boolean = false
+}
+
+case class isAverage(value: TriState) extends BooleanDecodeAttribute {
+  override val description: String = "For adder, does it need to take care of saturate. TODO: add to uop "
+}

t1/src/decoder/attribute/isCompress.scala

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]>
+
+package org.chipsalliance.t1.rtl.decoder.attribute
+
+import org.chipsalliance.t1.rtl.decoder.T1DecodePattern
+
+object isCompress {
+  def apply(t1DecodePattern: T1DecodePattern): isCompress =
+    Seq(
+      y _ -> Y,
+      n _ -> N,
+      dc _ -> DC
+    ).collectFirst {
+      case (fn, tri) if fn(t1DecodePattern) => isCompress(tri)
+    }.get
+
+  def y(t1DecodePattern: T1DecodePattern): Boolean = {
+    val allMatched = Seq(
+      "vcompress.vm",
+    )
+    allMatched.contains(t1DecodePattern.instruction)
+  }
+  def n(t1DecodePattern: T1DecodePattern): Boolean = {
+    val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i =>
+      !(y(t1DecodePattern) || dc(t1DecodePattern))
+    )
+    allMatched.contains(t1DecodePattern.instruction)
+  }
+
+  def dc(t1DecodePattern: T1DecodePattern): Boolean = false
+}
+
+case class isCompress(value: TriState) extends BooleanDecodeAttribute {
+  override val description: String = "lane will read data from vs2, send to Sequencer. then Sequencer will read vs1 for mask. use mask to compress data in vs2. and write to vd at last. "
+}