[t1rocket] skip check when spike/rtl reg write idx == 0

chipsalliance · Aug 14, 2024 · 9864864 · 9864864
1 parent d54cb7b
commit 9864864
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Showing 3 changed files with 15 additions and 19 deletions.
diff --git a/t1rocketemu/spike_rs/src/spike_event.rs b/t1rocketemu/spike_rs/src/spike_event.rs
@@ -406,29 +406,25 @@ impl SpikeEvent {
         // scalar rf
         let data = state.get_reg(self.rd_idx, false);
         self.is_rd_written = true;
-        if data != self.rd_bits {
-          trace!(
-            "ScalarRFChange: idx={}, change_from={}, change_to={data}",
-            self.rd_idx,
-            self.rd_bits
-          );
-          self.rd_bits = data;
-        }
+        self.rd_bits = data;
+        trace!(
+          "ScalarRFChange: idx={:02x}, data={:08x}",
+          self.rd_idx,
+          self.rd_bits
+        );
       }
       0b0001 => {
         let data = state.get_reg(self.rd_idx, true);
         self.is_rd_written = true;
-        if data != self.rd_bits {
-          trace!(
-            "FloatRFChange: idx={}, change_from={}, change_to={data}",
-            self.rd_idx,
-            self.rd_bits
-          );
-          self.rd_bits = data;
-        }
+        self.rd_bits = data;
+        trace!(
+          "FloatRFChange: idx={:02x}, data={:08x}",
+          self.rd_idx,
+          self.rd_bits
+        );
       }
       _ => trace!(
-        "UnknownRegChange, idx={}, spike detect unknown reg change",
+        "UnknownRegChange, idx={:02x}, spike detect unknown reg change",
         state.get_reg_write_index(idx)
       ),
     });

diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
@@ -181,7 +181,7 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
 
   // output the probes
   // rocket reg write
-  when(rocketProbe.rfWen)(
+  when(rocketProbe.rfWen && rocketProbe.rfWaddr =/= 0.U)(
     printf(
       cf"""{"event":"RegWrite","idx":${rocketProbe.rfWaddr},"data":"${rocketProbe.rfWdata}%x","cycle":${simulationTime}}\n"""
     )

diff --git a/t1rocketemu/test_common/src/spike_runner.rs b/t1rocketemu/test_common/src/spike_runner.rs
@@ -127,7 +127,7 @@ impl SpikeRunner {
   pub fn find_reg_write(&mut self) -> SpikeEvent {
     loop {
       let se = self.spike_step();
-      if se.is_scalar() && se.is_rd_written {
+      if se.is_scalar() && se.is_rd_written && se.rd_idx != 0 {
         return se;
       }
     }