[t1emu & t1rocketemu] rename ClockGen -> VerbatimModule

difftest/dpi_t1emu/src/lib.rs

@@ -44,7 +44,7 @@ impl OnlineArgs {
   }
 }
 
-// keep in sync with TestBench.ClockGen
+// keep in sync with TestBench.verbatimModule
 // the value is measured in simulation time unit
 pub const CYCLE_PERIOD: u64 = 20000;
 

difftest/dpi_t1rocketemu/src/lib.rs

@@ -32,7 +32,7 @@ impl OnlineArgs {
   }
 }
 
-// keep in sync with TestBench.ClockGen
+// keep in sync with TestBench.verbatimModule
 // the value is measured in simulation time unit
 pub const CYCLE_PERIOD: u64 = 20000;
 

t1emu/src/TestBench.scala

@@ -39,23 +39,23 @@ class TestBench(val parameter: T1Parameter)
   val om:         Property[ClassType]   = IO(Output(Property[omType.Type]()))
   om := omInstance.getPropertyReference
 
-  val clockGen = Module(new ExtModule {
+  val verbatimModule = Module(new ExtModule {
 
-    override def desiredName = "ClockGen"
+    override def desiredName = "VerbatimModule"
     val clock                = IO(Output(Bool()))
     val reset                = IO(Output(Bool()))
   })
-  def clock                  = clockGen.clock.asClock
-  def reset                  = clockGen.reset
-  override def implicitClock = clockGen.clock.asClock
-  override def implicitReset = clockGen.reset
+  def clock                  = verbatimModule.clock.asClock
+  def reset                  = verbatimModule.reset
+  override def implicitClock = verbatimModule.clock.asClock
+  override def implicitReset = verbatimModule.reset
   val dut: Instance[T1] = SerializableModuleGenerator(classOf[T1], parameter).instance()
 
   val simulationTime: UInt = RegInit(0.U(64.W))
   simulationTime := simulationTime + 1.U
 
-  dut.io.clock    := clockGen.clock.asClock
-  dut.io.reset    := clockGen.reset
+  dut.io.clock    := clock
+  dut.io.reset    := reset
   omInstance.t1In := Property(dut.io.om.asAnyClassType)
 
   // uint32_t -> svBitVecVal -> reference type with 7 length.

t1emu/vsrc/ClockGen.sv → t1emu/vsrc/VerbatimModule.sv

@@ -1,5 +1,8 @@
-module ClockGen(output reg clock, output reg reset);
+module VerbatimModule(output reg clock, output reg reset);
 
+  // This module contains everything we can not represent in Chisel currently,
+  // including clock gen, plusarg parsing, sim control, etc
+  //
   // plusargs: "T" denotes being present only if trace is enabled 
   //   +t1_elf_file       (required)   path to elf file, parsed in DPI side
   //   +t1_wave_path      (required T) path to wave dump file

t1rocketemu/src/TestBench.scala

@@ -39,18 +39,18 @@ class TestBench(val parameter: T1RocketTileParameter)
   val om:         Property[ClassType]   = IO(Output(Property[omType.Type]()))
   om := omInstance.getPropertyReference
 
-  val clockGen               = Module(new ExtModule {
-    override def desiredName = "ClockGen"
+  val verbatimModule         = Module(new ExtModule {
+    override def desiredName = "VerbatimModule"
     val clock                = IO(Output(Bool()))
     val reset                = IO(Output(Bool()))
     val initFlag             = IO(Output(Bool()))
     val idle                 = IO(Input(Bool()))
   })
-  def clock                  = clockGen.clock.asClock
-  def reset                  = clockGen.reset
-  def initFlag               = clockGen.initFlag
-  override def implicitClock = clockGen.clock.asClock
-  override def implicitReset = clockGen.reset
+  def clock                  = verbatimModule.clock.asClock
+  def reset                  = verbatimModule.reset
+  def initFlag               = verbatimModule.initFlag
+  override def implicitClock = verbatimModule.clock.asClock
+  override def implicitReset = verbatimModule.reset
   val dut: Instance[T1RocketTile] = SerializableModuleGenerator(classOf[T1RocketTile], parameter).instance()
   omInstance.t1RocketTileIn := Property(dut.io.om.asAnyClassType)
 
@@ -303,7 +303,7 @@ class TestBench(val parameter: T1RocketTileParameter)
   }
 
   // t1 quit
-  clockGen.idle := t1Probe.idle && rocketProbe.idle
+  verbatimModule.idle := t1Probe.idle && rocketProbe.idle
 
   // t1rocket ProfData
   layer.block(layers.Verification) {

t1rocketemu/vsrc/ClockGen.sv → t1rocketemu/vsrc/VerbatimModule.sv

@@ -1,10 +1,13 @@
-module ClockGen(
+module VerbatimModule(
   output reg clock,
   output reg reset,
   output reg initFlag,
   input  wire idle
 );
 
+  // This module contains everything we can not represent in Chisel currently,
+  // including clock gen, plusarg parsing, sim control, etc
+  //
   // plusargs: "T" denotes being present only if trace is enabled 
   //   +t1_elf_file       (required)   path to elf file, parsed in DPI side
   //   +t1_wave_path      (required T) path to wave dump file