[rocketv] fix fetch width.

chipsalliance · Jul 26, 2024 · 8cfdc8e · 8cfdc8e
1 parent 4662570
commit 8cfdc8e
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Showing 6 changed files with 26 additions and 17 deletions.
diff --git a/elaborator/src/rocketv/IBuf.scala b/elaborator/src/rocketv/IBuf.scala
@@ -16,7 +16,8 @@ object IBuf extends Elaborator {
     @arg(name = "entries") entries:                     Int,
     @arg(name = "vaddrBitsExtended") vaddrBitsExtended: Int,
     @arg(name = "bhtHistoryLength") bhtHistoryLength:   Option[Int],
-    @arg(name = "bhtCounterLength") bhtCounterLength:   Option[Int]) {
+    @arg(name = "bhtCounterLength") bhtCounterLength:   Option[Int],
+    @arg(name = "fetchWidth") fetchWidth:               Int) {
     def convert: IBufParameter = IBufParameter(
       useAsyncReset,
       xLen,
@@ -25,7 +26,8 @@ object IBuf extends Elaborator {
       entries,
       vaddrBitsExtended,
       bhtHistoryLength,
-      bhtCounterLength
+      bhtCounterLength,
+      fetchWidth
     )
   }
 

diff --git a/rocketv/src/Bundle.scala b/rocketv/src/Bundle.scala
@@ -551,9 +551,9 @@ class FrontendResp(
                     bhtHistoryLength:  Option[Int],
                     bhtCounterLength:  Option[Int],
                     vaddrBitsExtended: Int,
-                    coreInstBits:      Int)
+                    coreInstBits:      Int,
+                    fetchWidth: Int)
   extends Bundle {
-  def fetchWidth = 1
   val btb = new BTBResp(vaddrBits, entries, bhtHistoryLength: Option[Int], bhtCounterLength: Option[Int])
   val pc = UInt(vaddrBitsExtended.W) // ID stage PC
   val data = UInt((fetchWidth * coreInstBits).W)
@@ -1384,12 +1384,12 @@ class FrontendPerfEvents extends Bundle {
   val tlbMiss = Bool()
 }
 
-class FrontendIO(vaddrBitsExtended: Int, vaddrBits: Int, asidBits: Int, entries: Int, bhtHistoryLength: Option[Int], bhtCounterLength: Option[Int], coreInstBits: Int) extends Bundle {
+class FrontendIO(vaddrBitsExtended: Int, vaddrBits: Int, asidBits: Int, entries: Int, bhtHistoryLength: Option[Int], bhtCounterLength: Option[Int], coreInstBits: Int, fetchWidth: Int) extends Bundle {
   val might_request = Output(Bool())
   val clock_enabled = Input(Bool())
   val req = Valid(new FrontendReq(vaddrBitsExtended))
   val sfence = Valid(new SFenceReq(vaddrBits, asidBits))
-  val resp = Flipped(Decoupled(new FrontendResp(vaddrBits, entries, bhtHistoryLength, bhtCounterLength, vaddrBitsExtended, coreInstBits)))
+  val resp = Flipped(Decoupled(new FrontendResp(vaddrBits, entries, bhtHistoryLength, bhtCounterLength, vaddrBitsExtended, coreInstBits, fetchWidth)))
   val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W)))
   val btb_update = Valid(new BTBUpdate(vaddrBits, entries, bhtHistoryLength, bhtCounterLength))
   val bht_update = Valid(new BHTUpdate(bhtHistoryLength, bhtCounterLength, vaddrBits))
@@ -1401,8 +1401,8 @@ class FrontendIO(vaddrBitsExtended: Int, vaddrBits: Int, asidBits: Int, entries:
 }
 
 // Non-diplomatic version of Frontend
-class FrontendBundle(vaddrBitsExtended: Int, vaddrBits: Int, asidBits: Int, entries: Int, bhtHistoryLength: Option[Int], bhtCounterLength: Option[Int], coreInstBits: Int, nPMPs: Int, vpnBits: Int, paddrBits: Int, pgLevels: Int, xLen: Int, maxPAddrBits: Int, pgIdxBits: Int, hasCorrectable: Boolean, hasUncorrectable: Boolean) extends Bundle {
-  val cpu = Flipped(new FrontendIO(vaddrBitsExtended, vaddrBits, asidBits, entries, bhtHistoryLength, bhtCounterLength, coreInstBits))
+class FrontendBundle(vaddrBitsExtended: Int, vaddrBits: Int, asidBits: Int, entries: Int, bhtHistoryLength: Option[Int], bhtCounterLength: Option[Int], coreInstBits: Int, nPMPs: Int, vpnBits: Int, paddrBits: Int, pgLevels: Int, xLen: Int, maxPAddrBits: Int, pgIdxBits: Int, hasCorrectable: Boolean, hasUncorrectable: Boolean, fetchWidth: Int) extends Bundle {
+  val cpu = Flipped(new FrontendIO(vaddrBitsExtended, vaddrBits, asidBits, entries, bhtHistoryLength, bhtCounterLength, coreInstBits, fetchWidth))
   val ptw = new TLBPTWIO(nPMPs, vpnBits, paddrBits, vaddrBits, pgLevels, xLen, maxPAddrBits, pgIdxBits)
   val errors = new ICacheErrors(hasCorrectable, hasUncorrectable, paddrBits)
 }

diff --git a/rocketv/src/FetchQueue.scala b/rocketv/src/FetchQueue.scala
@@ -22,15 +22,17 @@ case class FetchQueueParameter(
   bhtHistoryLength:  Option[Int],
   bhtCounterLength:  Option[Int],
   vaddrBitsExtended: Int,
-  coreInstBits:      Int)
+  coreInstBits:      Int,
+  fetchWidth:        Int)
     extends SerializableModuleParameter {
   def gen = new FrontendResp(
     vaddrBits,
     respEntries,
     bhtHistoryLength,
     bhtCounterLength,
     vaddrBitsExtended,
-    coreInstBits
+    coreInstBits,
+    fetchWidth
   )
 }
 

diff --git a/rocketv/src/Frontend.scala b/rocketv/src/Frontend.scala
@@ -195,6 +195,7 @@ case class FrontendParameter(
     bhtCounterLength = bhtCounterLength,
     vaddrBitsExtended = vaddrBitsExtended,
     coreInstBits = coreInstBits,
+    fetchWidth = fetchWidth
   )
 }
 
@@ -218,7 +219,8 @@ class FrontendInterface(parameter: FrontendParameter) extends Bundle {
     parameter.maxPAddrBits,
     parameter.pgIdxBits,
     parameter.hasCorrectable,
-    parameter.hasUncorrectable
+    parameter.hasUncorrectable,
+    parameter.fetchWidth
   )
   val instructionFetchAXI: AXI4ROIrrevocable =
     org.chipsalliance.amba.axi4.bundle.AXI4ROIrrevocable(parameter.instructionFetchParameter)

diff --git a/rocketv/src/IBuf.scala b/rocketv/src/IBuf.scala
@@ -21,9 +21,9 @@ case class IBufParameter(
                           // TODO: have a better way to calculate it, like what we did in the CSR...
                           vaddrBitsExtended: Int,
                           bhtHistoryLength:  Option[Int],
-                          bhtCounterLength:  Option[Int]
+                          bhtCounterLength:  Option[Int],
+                          fetchWidth:        Int
                         ) extends SerializableModuleParameter {
-  val fetchWidth: Int = 1
   val retireWidth: Int = 1
   val coreInstBits: Int = if (usingCompressed) 16 else 32
   val coreInstBytes: Int = coreInstBits / 8
@@ -40,7 +40,8 @@ class IBufInterface(parameter: IBufParameter) extends Bundle {
         parameter.bhtHistoryLength,
         parameter.bhtCounterLength,
         parameter.vaddrBitsExtended,
-        parameter.coreInstBits
+        parameter.coreInstBits,
+        parameter.fetchWidth
       )
     )
   )

diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
@@ -147,7 +147,7 @@ case class RocketParameter(
   def usingNMI = hasInstructionSet("rv_smrnmi")
 
   // calculated parameter
-  def fetchWidth: Int = 1
+  def fetchWidth: Int = if (usingCompressed) 2 else 1
 
   def resetVectorLen: Int = {
     val externalLen = paddrBits
@@ -247,7 +247,8 @@ case class RocketParameter(
     btbEntries,
     vaddrBitsExtended,
     bhtHistoryLength,
-    bhtCounterLength
+    bhtCounterLength,
+    fetchWidth
   )
   val breakpointUnitParameter: BreakpointUnitParameter = BreakpointUnitParameter(
     nBreakpoints,
@@ -290,7 +291,8 @@ class RocketInterface(parameter: RocketParameter) extends Bundle {
     parameter.btbEntries,
     parameter.bhtHistoryLength,
     parameter.bhtCounterLength,
-    parameter.coreInstBits
+    parameter.coreInstBits,
+    parameter.fetchWidth
   )
 
   val dmem = new HellaCacheIO(