[rtl] redesign T1Interface

ipemu/src/TestBench.scala

@@ -112,40 +112,38 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
   val issue = WireDefault(0.U.asTypeOf(new Issue))
   val fence = RegInit(false.B)
   val outstanding = RegInit(0.U(4.W))
-  val doIssue: Bool = dut.io.request.ready && !fence
-  outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.response.valid
-  fence := Mux(doIssue, issue.meta === 2.U, fence && !dut.io.response.valid && !(outstanding === 0.U))
+  val doIssue: Bool = dut.io.issue.ready && !fence
+  outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.issue.valid
+  // TODO: refactor driver to spawn 3 scoreboards for record different retirement.
+  val t1Probe = probe.read(dut.io.t1Probe)
+  fence := Mux(doIssue, issue.meta === 2.U, fence && !t1Probe.retireValid && !(outstanding === 0.U))
 
   issue := RawClockedNonVoidFunctionCall("issue_vector_instruction", new Issue)(
     clock,
     doIssue
   )
-  dut.io.request.bits.instruction := issue.instruction
-  dut.io.request.bits.src1Data := issue.src1Data
-  dut.io.request.bits.src2Data := issue.src2Data
-  dut.io.csrInterface.vlmul := issue.vtype(2, 0)
-  dut.io.csrInterface.vSew := issue.vtype(5, 3)
-  dut.io.csrInterface.vta := issue.vtype(6)
-  dut.io.csrInterface.vma := issue.vtype(7)
-  dut.io.csrInterface.vl := issue.vl
-  dut.io.csrInterface.vStart := issue.vstart
-  dut.io.csrInterface.vxrm := issue.vcsr(2, 1)
-
-  dut.io.csrInterface.ignoreException := 0.U
-  dut.io.storeBufferClear := true.B
-  dut.io.request.valid := issue.meta === 1.U
+  dut.io.issue.bits.instruction := issue.instruction
+  dut.io.issue.bits.rs1Data := issue.src1Data
+  dut.io.issue.bits.rs2Data := issue.src2Data
+  dut.io.issue.bits.vtype := issue.vtype
+  dut.io.issue.bits.vl := issue.vl
+  dut.io.issue.bits.vstart := issue.vstart
+  dut.io.issue.bits.vcsr := issue.vcsr
+  dut.io.issue.valid := issue.meta === 1.U
   when(issue.meta =/= 0.U && issue.meta =/= 1.U && issue.meta =/= 2.U) {
     stop(cf"""{"event":"SimulationStop","reason": ${issue.meta},"cycle":${simulationTime}}\n""")
   }
   val retire = Wire(new Retire)
-  retire.rd := dut.io.response.bits.rd.bits
-  retire.data := dut.io.response.bits.data
-  retire.writeRd := dut.io.response.bits.rd.valid
-  retire.vxsat := dut.io.response.bits.vxsat
-  RawClockedVoidFunctionCall("retire_vector_instruction")(clock, dut.io.response.valid, retire)
+  retire.rd := dut.io.retire.rd.bits.rdAddress
+  retire.data := dut.io.retire.rd.bits.rdData
+  retire.writeRd := dut.io.retire.rd.valid
+  retire.vxsat := dut.io.retire.csr.bits.vxsat
+  // TODO:
+  //  retire.fflag := dut.io.retire.csr.bits.fflag
+  RawClockedVoidFunctionCall("retire_vector_instruction")(clock, t1Probe.retireValid, retire)
   val dummy = Wire(Bool())
   dummy := false.B
-  RawClockedVoidFunctionCall("retire_vector_mem")(clock, dut.io.response.bits.mem && dut.io.response.valid, dummy)
+  RawClockedVoidFunctionCall("retire_vector_mem")(clock, dut.io.retire.mem.valid, dummy)
 
   // Memory Drivers
   Seq(
@@ -201,8 +199,6 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
       wire
   }
 
-  val t1Probe = probe.read(dut.io.t1Probe)
-
   // vrf write
   laneVrfProbes.zipWithIndex.foreach {
     case (lane, i) =>
@@ -225,13 +221,13 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
     )
   )
   // issue
-  when(dut.io.request.fire)(
+  when(dut.io.issue.fire)(
     printf(cf"""{"event":"Issue","idx":${t1Probe.instructionCounter},"cycle":${simulationTime}}\n""")
   )
   // check rd
-  when(dut.io.response.bits.rd.valid)(
+  when(dut.io.retire.rd.valid)(
     printf(
-      cf"""{"event":"CheckRd","data":"${dut.io.response.bits.data}%x","issue_idx":${t1Probe.responseCounter},"cycle":${simulationTime}}\n"""
+      cf"""{"event":"CheckRd","data":"${dut.io.retire.rd.bits.rdData}%x","issue_idx":${t1Probe.responseCounter},"cycle":${simulationTime}}\n"""
     )
   )
   // lsu enq

t1/src/Bundles.scala

@@ -10,23 +10,6 @@ import org.chipsalliance.t1.rtl.decoder.Decoder
 import org.chipsalliance.t1.rtl.lsu.LSUParameter
 import org.chipsalliance.t1.rtl.vrf.VRFParam
 
-/** Interface from CPU. */
-class VRequest(xLen: Int) extends Bundle {
-
-  /** instruction fetched by scalar processor. */
-  val instruction: UInt = UInt(32.W)
-
-  /** data read from scalar RF RS1.
-    * TODO: rename to rs1Data
-    */
-  val src1Data: UInt = UInt(xLen.W)
-
-  /** data read from scalar RF RS2.
-    * TODO: rename to rs2Data
-    */
-  val src2Data: UInt = UInt(xLen.W)
-}
-
 /** Interface to CPU. */
 class VResponse(xLen: Int) extends Bundle {
 
@@ -325,9 +308,6 @@ class CSRInterface(vlWidth: Int) extends Bundle {
     * we always keep the undisturbed behavior, since there is no rename here.
     */
   val vma: Bool = Bool()
-
-  /** TODO: remove it. */
-  val ignoreException: Bool = Bool()
 }
 
 /** [[Lane]] -> [[T1]], response for [[LaneRequest]] */
@@ -501,20 +481,11 @@ class VRFWriteReport(param: VRFParam) extends Bundle {
   val state = new VRFInstructionState
 }
 
-/** 为了decode, 指令需要在入口的时候打一拍, 这是需要保存的信息 */
 class InstructionPipeBundle(parameter: T1Parameter) extends Bundle {
-  // 原始指令信息
-  val request: VRequest = new VRequest(parameter.xLen)
-  // decode 的结果
+  val issue: T1Issue = new T1Issue(parameter.xLen, parameter.vLen)
   val decodeResult: DecodeBundle = new DecodeBundle(Decoder.allFields(parameter.decoderParam))
-  // 这条指令被vector分配的index
   val instructionIndex: UInt = UInt(parameter.instructionIndexBits.W)
-  // 指令的csr信息
-  val csr = new CSRInterface(parameter.laneParam.vlMaxBits)
-  // 有写v0的风险
   val vdIsV0: Bool = Bool()
-
-  // How many bytes of registers will be written by one instruction?
   val writeByte: UInt = UInt(parameter.laneParam.vlMaxBits.W)
 }
 
@@ -711,3 +682,44 @@ final class EmptyBundle extends Bundle
 class VRFReadPipe(size: BigInt) extends Bundle {
   val address: UInt = UInt(log2Ceil(size).W)
 }
+
+class T1Issue(xLen: Int, vlWidth: Int) extends Bundle {
+
+  /** instruction fetched by scalar processor. */
+  val instruction: UInt = UInt(32.W)
+
+  /** data read from scalar RF RS1. */
+  val rs1Data: UInt = UInt(xLen.W)
+
+  /** data read from scalar RF RS2. */
+  val rs2Data: UInt = UInt(xLen.W)
+  val vtype: UInt = UInt(32.W)
+  val vl:    UInt = UInt(32.W)
+  val vstart: UInt = UInt(32.W)
+  val vcsr: UInt = UInt(32.W)
+}
+
+object T1Issue {
+  def vlmul(issue: T1Issue) = issue.vtype(2, 0)
+  def vsew(issue: T1Issue) = issue.vtype(5, 3)
+  def vta(issue: T1Issue) = issue.vtype(6)
+  def vma(issue: T1Issue) = issue.vtype(7)
+  def vxrm(issue: T1Issue) = issue.vcsr(2, 1)
+}
+
+class T1RdRetire(xLen: Int) extends Bundle {
+  val rdAddress: UInt = UInt(5.W)
+  val rdData:    UInt = UInt(xLen.W)
+  val isFp:      Bool = Bool()
+}
+
+class T1CSRRetire extends Bundle {
+  val vxsat: UInt = UInt(32.W)
+  val fflag: UInt = UInt(32.W)
+}
+
+class T1Retire(xLen: Int) extends Bundle {
+  val rd:  ValidIO[T1RdRetire] = Valid(new T1RdRetire(xLen))
+  val csr: ValidIO[T1CSRRetire] = Valid(new T1CSRRetire)
+  val mem: ValidIO[EmptyBundle] = Valid(new EmptyBundle)
+}