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[rtl] public all modules
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sequencer committed Aug 29, 2024
1 parent a28eaca commit 871c362
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Showing 29 changed files with 40 additions and 11 deletions.
3 changes: 2 additions & 1 deletion rocketv/src/ALU.scala
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Expand Up @@ -56,7 +56,8 @@ class ALUInterface(parameter: ALUParameter) extends Bundle {
@instantiable
class ALU(val parameter: ALUParameter)
extends FixedIORawModule(new ALUInterface(parameter))
with SerializableModule[ALUParameter] {
with SerializableModule[ALUParameter]
with Public {
// compatibility layer
val aluFn = parameter
val xLen = parameter.xLen
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3 changes: 2 additions & 1 deletion rocketv/src/AMOALU.scala
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Expand Up @@ -37,7 +37,8 @@ class AMOALUInterface(parameter: AMOALUParameter) extends Bundle {
@instantiable
class AMOALU(val parameter: AMOALUParameter)
extends FixedIORawModule(new AMOALUInterface(parameter))
with SerializableModule[AMOALUParameter] {
with SerializableModule[AMOALUParameter]
with Public {
val M_XA_MAX = parameter.M_XA_MAX
val M_XA_MAXU = parameter.M_XA_MAXU
val M_XA_MIN = parameter.M_XA_MIN
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1 change: 1 addition & 0 deletions rocketv/src/BTB.scala
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Expand Up @@ -91,6 +91,7 @@ class BTBInterface(parameter: BTBParameter) extends Bundle {
class BTB(val parameter: BTBParameter)
extends FixedIORawModule(new BTBInterface(parameter))
with SerializableModule[BTBParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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3 changes: 2 additions & 1 deletion rocketv/src/Breakpoint.scala
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Expand Up @@ -32,7 +32,8 @@ class BreakpointUnitInterface(parameter: BreakpointUnitParameter) extends Bundle
@instantiable
class BreakpointUnit(val parameter: BreakpointUnitParameter)
extends FixedIORawModule(new BreakpointUnitInterface(parameter))
with SerializableModule[BreakpointUnitParameter] {
with SerializableModule[BreakpointUnitParameter]
with Public {
io.xcpt_if := false.B
io.xcpt_ld := false.B
io.xcpt_st := false.B
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1 change: 1 addition & 0 deletions rocketv/src/CSR.scala
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Expand Up @@ -288,6 +288,7 @@ class CSRInterface(parameter: CSRParameter) extends Bundle {
class CSR(val parameter: CSRParameter)
extends FixedIORawModule(new CSRInterface(parameter))
with SerializableModule[CSRParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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3 changes: 2 additions & 1 deletion rocketv/src/Decoder.scala
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Expand Up @@ -963,7 +963,8 @@ case class RocketDecodePattern(instruction: Instruction) extends DecodePattern {
@instantiable
class Decoder(val parameter: DecoderParameter)
extends FixedIORawModule(new DecoderInterface(parameter))
with SerializableModule[DecoderParameter] {
with SerializableModule[DecoderParameter]
with Public {
io.output := parameter.table.decode(io.instruction)
}

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1 change: 1 addition & 0 deletions rocketv/src/FPU.scala
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Expand Up @@ -53,6 +53,7 @@ class FPUInterface(parameter: FPUParameter) extends Bundle {
class FPU(val parameter: FPUParameter)
extends FixedIORawModule(new FPUInterface(parameter))
with SerializableModule[FPUParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/FetchQueue.scala
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Expand Up @@ -48,6 +48,7 @@ class FetchQueueInterface(parameter: FetchQueueParameter) extends Bundle {
class FetchQueue(val parameter: FetchQueueParameter)
extends FixedIORawModule(new FetchQueueInterface(parameter))
with SerializableModule[FetchQueueParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/Frontend.scala
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Expand Up @@ -233,6 +233,7 @@ class FrontendInterface(parameter: FrontendParameter) extends Bundle {
class Frontend(val parameter: FrontendParameter)
extends FixedIORawModule(new FrontendInterface(parameter))
with SerializableModule[FrontendParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/HellaCache.scala
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Expand Up @@ -317,6 +317,7 @@ class HellaCacheInterface(parameter: HellaCacheParameter) extends Bundle {
class HellaCache(val parameter: HellaCacheParameter)
extends FixedIORawModule(new HellaCacheInterface(parameter))
with SerializableModule[HellaCacheParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/HellaCacheArbiter.scala
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Expand Up @@ -109,6 +109,7 @@ class HellaCacheArbiterInterface(parameter: HellaCacheArbiterParameter) extends
class HellaCacheArbiter(val parameter: HellaCacheArbiterParameter)
extends FixedIORawModule(new HellaCacheArbiterInterface(parameter))
with SerializableModule[HellaCacheArbiterParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/IBuf.scala
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Expand Up @@ -64,6 +64,7 @@ class IBufInterface(parameter: IBufParameter) extends Bundle {
class IBuf(val parameter: IBufParameter)
extends FixedIORawModule(new IBufInterface(parameter))
with SerializableModule[IBufParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/ICache.scala
Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,7 @@ class ICacheInterface(parameter: ICacheParameter) extends Bundle {
class ICache(val parameter: ICacheParameter)
extends FixedIORawModule(new ICacheInterface(parameter))
with SerializableModule[ICacheParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/MulDiv.scala
Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,7 @@ class MulDivInterface(parameter: MulDivParameter) extends Bundle {
class MulDiv(val parameter: MulDivParameter)
extends FixedIORawModule(new MulDivInterface(parameter))
with SerializableModule[MulDivParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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3 changes: 2 additions & 1 deletion rocketv/src/PMA.scala
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,8 @@ class PMACheckerInterface(parameter: PMACheckerParameter) extends Bundle {
@instantiable
class PMAChecker(val parameter: PMACheckerParameter)
extends FixedIORawModule(new PMACheckerInterface(parameter))
with SerializableModule[PMACheckerParameter] {
with SerializableModule[PMACheckerParameter]
with Public {
// check exist a slave can consume this address.
val legal_address = parameter.legal.matches(io.paddr)
io.resp.cacheable := legal_address && (if(parameter.cacheable.isEmpty) false.B else parameter.cacheable.matches(io.paddr))
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3 changes: 2 additions & 1 deletion rocketv/src/PMP.scala
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Expand Up @@ -34,7 +34,8 @@ class PMPCheckerInterface(parameter: PMPCheckerParameter) extends Bundle {
@instantiable
class PMPChecker(val parameter: PMPCheckerParameter)
extends FixedIORawModule(new PMPCheckerInterface(parameter))
with SerializableModule[PMPCheckerParameter] {
with SerializableModule[PMPCheckerParameter]
with Public {

val paddrBits = parameter.paddrBits
val pmpGranularity = parameter.pmpGranularity
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3 changes: 2 additions & 1 deletion rocketv/src/PTW.scala
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Expand Up @@ -170,7 +170,8 @@ class PTW(val parameter: PTWParameter)
extends FixedIORawModule(new PTWInterface(parameter))
with SerializableModule[PTWParameter]
with ImplicitClock
with ImplicitReset {
with ImplicitReset
with Public {
override protected def implicitClock: Clock = io.clock
override protected def implicitReset: Reset = io.reset

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1 change: 1 addition & 0 deletions rocketv/src/PipelinedMultiplier.scala
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ class PipelinedMultiplierInterface(parameter: PipelinedMultiplierParameter) exte
class PipelinedMultiplier(val parameter: PipelinedMultiplierParameter)
extends FixedIORawModule(new PipelinedMultiplierInterface(parameter))
with SerializableModule[PipelinedMultiplierParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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3 changes: 2 additions & 1 deletion rocketv/src/RVCExpander.scala
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Expand Up @@ -168,7 +168,8 @@ class RVCExpanderInterface(parameter: RVCExpanderParameter) extends Bundle {
@instantiable
class RVCExpander(val parameter: RVCExpanderParameter)
extends FixedIORawModule(new RVCExpanderInterface(parameter))
with SerializableModule[RVCExpanderParameter] {
with SerializableModule[RVCExpanderParameter]
with Public {
val usingCompressed = parameter.usingCompressed
val useAddiForMv = parameter.useAddiForMv
val xLen = parameter.xLen
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3 changes: 2 additions & 1 deletion rocketv/src/RocketCore.scala
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Expand Up @@ -366,7 +366,8 @@ class Rocket(val parameter: RocketParameter)
extends FixedIORawModule(new RocketInterface(parameter))
with SerializableModule[RocketParameter]
with ImplicitClock
with ImplicitReset {
with ImplicitReset
with Public {
override protected def implicitClock: Clock = io.clock
override protected def implicitReset: Reset = io.reset
val csr: Instance[CSR] = Instantiate(new CSR(parameter.csrParameter))
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3 changes: 2 additions & 1 deletion rocketv/src/RocketTile.scala
Original file line number Diff line number Diff line change
Expand Up @@ -401,7 +401,8 @@ class RocketTileInterface(parameter: RocketTileParameter) extends Bundle {

class RocketTile(val parameter: RocketTileParameter)
extends FixedIORawModule(new RocketTileInterface(parameter))
with SerializableModule[RocketTileParameter] {
with SerializableModule[RocketTileParameter]
with Public {
val rocket: Instance[Rocket] = Instantiate(new Rocket(parameter.rocketParameter))
val frontend: Instance[Frontend] = Instantiate(new Frontend(parameter.frontendParameter))
val hellaCache: Instance[HellaCache] = Instantiate(new HellaCache(parameter.hellaCacheParameter))
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1 change: 1 addition & 0 deletions rocketv/src/TLB.scala
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Expand Up @@ -122,6 +122,7 @@ class TLBInterface(parameter: TLBParameter) extends Bundle {
class TLB(val parameter: TLBParameter)
extends FixedIORawModule(new TLBInterface(parameter))
with SerializableModule[TLBParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/fpu/FPToFP.scala
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@ class FPToFPInterface(parameter: FPToFPParameter) extends Bundle {
class FPToFP(val parameter: FPToFPParameter)
extends FixedIORawModule(new FPToFPInterface(parameter))
with SerializableModule[FPToFPParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/fpu/FPToInt.scala
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Expand Up @@ -30,6 +30,7 @@ class FPToIntInterface(parameter: FPToIntParameter) extends Bundle {
class FPToInt(val parameter: FPToIntParameter)
extends FixedIORawModule(new FPToIntInterface(parameter))
with SerializableModule[FPToIntParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/fpu/FPUFMAPipe.scala
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@ class FPUFMAPipeInterface(parameter: FPUFMAPipeParameter) extends Bundle {
class FPUFMAPipe(val parameter: FPUFMAPipeParameter)
extends FixedIORawModule(new FPUFMAPipeInterface(parameter))
with SerializableModule[FPUFMAPipeParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/fpu/IntToFP.scala
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@ class IntToFPInterface(parameter: IntToFPParameter) extends Bundle {
class IntToFP(val parameter: IntToFPParameter)
extends FixedIORawModule(new IntToFPInterface(parameter))
with SerializableModule[IntToFPParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions rocketv/src/fpu/MulAddRecFNPipe.scala
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,7 @@ class MulAddRecFNPipeInterface(parameter: MulAddRecFNPipeParameter) extends Bund
class MulAddRecFNPipe(val parameter: MulAddRecFNPipeParameter)
extends FixedIORawModule(new MulAddRecFNPipeInterface(parameter))
with SerializableModule[MulAddRecFNPipeParameter]
with Public
with ImplicitClock
with ImplicitReset {
override protected def implicitClock: Clock = io.clock
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1 change: 1 addition & 0 deletions t1/src/T1.scala
Original file line number Diff line number Diff line change
Expand Up @@ -344,6 +344,7 @@ class T1Interface(parameter: T1Parameter) extends Record {
class T1(val parameter: T1Parameter)
extends FixedIORawModule(new T1Interface(parameter))
with SerializableModule[T1Parameter]
with Public
with ImplicitClock
with ImplicitReset {
def implicitClock: Clock = io.clock
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3 changes: 2 additions & 1 deletion t1rocket/src/T1RocketTile.scala
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Expand Up @@ -470,7 +470,8 @@ class T1RocketTileInterface(parameter: T1RocketTileParameter) extends Bundle {

class T1RocketTile(val parameter: T1RocketTileParameter)
extends FixedIORawModule(new T1RocketTileInterface(parameter))
with SerializableModule[T1RocketTileParameter] {
with SerializableModule[T1RocketTileParameter]
with Public {
val rocket: Instance[Rocket] = Instantiate(new Rocket(parameter.rocketParameter))
val frontend: Instance[Frontend] = Instantiate(new Frontend(parameter.frontendParameter))
val hellaCache: Instance[HellaCache] = Instantiate(new HellaCache(parameter.hellaCacheParameter))
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