[rtl] fix gatherNeedRead.

chipsalliance · Nov 21, 2024 · 8670ed5 · 8670ed5
1 parent 1039719
commit 8670ed5
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -540,7 +540,7 @@ class T1(val parameter: T1Parameter)
     parameter.instructionIndexBits
   )
 
-  val gatherNeedRead: Bool = requestRegDequeue.valid && decodeResult(Decoder.gather)
+  val gatherNeedRead: Bool = requestRegDequeue.valid && decodeResult(Decoder.gather) && !decodeResult(Decoder.vtype)
 
   /** state machine register for each instruction. */
   val slots: Seq[InstructionControl] = Seq.tabulate(parameter.chainingSize) { index =>