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[chore] reformat all t1 modules
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Signed-off-by: Avimitin <[email protected]>
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@Avimitin @sequencer
Avimitin authored and sequencer committed Oct 6, 2024
1 parent 5ed4f61 commit 7bd42e0
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Showing 35 changed files with 726 additions and 621 deletions.
12 changes: 6 additions & 6 deletions build.sc
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Original file line number Diff line number Diff line change
Expand Up @@ -142,7 +142,7 @@ trait T1Rocket extends millbuild.common.T1RocketModule with ScalafmtModule {

object t1emu extends T1Emulator

trait T1Emulator extends millbuild.common.T1EmulatorModule {
trait T1Emulator extends millbuild.common.T1EmulatorModule with ScalafmtModule {
def scalaVersion = T(v.scala)

def t1Module = t1
Expand All @@ -153,7 +153,7 @@ trait T1Emulator extends millbuild.common.T1EmulatorModule {
def chiselIvy = None
}

object rocketemu extends RocketEmulator
object rocketemu extends RocketEmulator

trait RocketEmulator extends millbuild.common.RocketEmulatorModule with ScalafmtModule {
def scalaVersion = T(v.scala)
Expand All @@ -168,7 +168,7 @@ trait RocketEmulator extends millbuild.common.RocketEmulatorModule with Scalafmt

object t1rocketemu extends T1RocketEmulator

trait T1RocketEmulator extends millbuild.common.T1RocketEmulatorModule {
trait T1RocketEmulator extends millbuild.common.T1RocketEmulatorModule with ScalafmtModule {
def scalaVersion = T(v.scala)

def t1rocketModule = t1rocket
Expand All @@ -192,7 +192,7 @@ trait PanamaConverter extends millbuild.dependencies.chisel.build.PanamaConverte
// Module to generate RTL from json config
object elaborator extends Elaborator

trait Elaborator extends millbuild.common.ElaboratorModule {
trait Elaborator extends millbuild.common.ElaboratorModule with ScalafmtModule {
def scalaVersion = T(v.scala)

def panamaconverterModule = panamaconverter
Expand All @@ -218,7 +218,7 @@ trait Elaborator extends millbuild.common.ElaboratorModule {

object omreaderlib extends OMReaderLib

trait OMReaderLib extends millbuild.common.OMReaderLibModule {
trait OMReaderLib extends millbuild.common.OMReaderLibModule with ScalafmtModule {
def scalaVersion = T(v.scala)

def panamaconverterModule = panamaconverter
Expand All @@ -235,7 +235,7 @@ trait OMReaderLib extends millbuild.common.OMReaderLibModule {

object omreader extends OMReader

trait OMReader extends millbuild.common.OMReaderModule {
trait OMReader extends millbuild.common.OMReaderModule with ScalafmtModule {
def scalaVersion = T(v.scala)

def panamaconverterModule = panamaconverter
Expand Down
47 changes: 25 additions & 22 deletions elaborator/src/Elaborator.scala
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Expand Up @@ -17,45 +17,48 @@ trait Elaborator {
}

def configImpl[P <: SerializableModuleParameter: universe.TypeTag](
parameter: P
)(implicit rwP: upickle.default.Writer[P]) = os.write.over(
parameter: P
)(
implicit rwP: upickle.default.Writer[P]
) = os.write.over(
os.pwd / s"${getClass.getSimpleName.replace("$", "")}.json",
upickle.default.write(parameter)
)

def designImpl[
M <: SerializableModule[P]: universe.TypeTag,
P <: SerializableModuleParameter: universe.TypeTag
](parameter: os.Path, runFirtool: Boolean)(implicit
rwP: upickle.default.Reader[P]
def designImpl[M <: SerializableModule[P]: universe.TypeTag, P <: SerializableModuleParameter: universe.TypeTag](
parameter: os.Path,
runFirtool: Boolean
)(
implicit
rwP: upickle.default.Reader[P]
) = {
var fir: firrtl.ir.Circuit = null
val annos = Seq(
val annos = Seq(
new chisel3.stage.phases.Elaborate,
new chisel3.stage.phases.Convert
).foldLeft(
Seq(
chisel3.stage.ChiselGeneratorAnnotation(() =>
SerializableModuleGenerator(
runtimeMirror(getClass.getClassLoader)
.runtimeClass(typeOf[M].typeSymbol.asClass)
.asInstanceOf[Class[M]],
upickle.default.read[P](os.read(parameter))
).module().asInstanceOf[RawModule]
)
): firrtl.AnnotationSeq
) { case (annos, stage) => stage.transform(annos) }
Seq(
chisel3.stage.ChiselGeneratorAnnotation(() =>
SerializableModuleGenerator(
runtimeMirror(getClass.getClassLoader)
.runtimeClass(typeOf[M].typeSymbol.asClass)
.asInstanceOf[Class[M]],
upickle.default.read[P](os.read(parameter))
).module().asInstanceOf[RawModule]
)
): firrtl.AnnotationSeq
) { case (annos, stage) => stage.transform(annos) }
.flatMap {
case firrtl.stage.FirrtlCircuitAnnotation(circuit) =>
fir = circuit
None
case _: chisel3.stage.DesignAnnotation[_] => None
case _: chisel3.stage.ChiselCircuitAnnotation => None
case a => Some(a)
case a => Some(a)
}
val annoJsonFile = os.pwd / s"${fir.main}.anno.json"
val firFile = os.pwd / s"${fir.main}.fir"
val svFile = os.pwd / s"${fir.main}.sv"
val firFile = os.pwd / s"${fir.main}.fir"
val svFile = os.pwd / s"${fir.main}.sv"
os.write.over(firFile, fir.serialize)
os.write.over(
annoJsonFile,
Expand Down
10 changes: 5 additions & 5 deletions elaborator/src/Main.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ object Main {
@arg(name = "target-dir", short = 't') targetDir: os.Path,
@arg(name = "binder-mlirbc-out") binderMlirbcOut: Option[String] = None) {
def elaborate(gen: () => chisel3.RawModule): Unit = {
var fir: firrtl.ir.Circuit = null
var fir: firrtl.ir.Circuit = null
var panamaCIRCTConverter: chisel3.panamaconverter.PanamaCIRCTConverter = null

val annos = Seq(
Expand All @@ -41,7 +41,7 @@ object Main {
): firrtl.AnnotationSeq
) { case (annos, stage) => stage.transform(annos) }
.flatMap {
case firrtl.stage.FirrtlCircuitAnnotation(circuit) =>
case firrtl.stage.FirrtlCircuitAnnotation(circuit) =>
if (binderMlirbcOut.isEmpty) fir = circuit
None
case chisel3.panamaconverter.stage.PanamaCIRCTConverterAnnotation(converter) =>
Expand All @@ -56,7 +56,7 @@ object Main {
binderMlirbcOut match {
case Some(outFile) =>
os.write(targetDir / s"$outFile.mlirbc", panamaCIRCTConverter.mlirBytecodeStream)
case None =>
case None =>
os.write(targetDir / s"${fir.main}.fir", fir.serialize)
os.write(targetDir / s"${fir.main}.anno.json", firrtl.annotations.JsonProtocol.serialize(annos))
}
Expand Down Expand Up @@ -95,8 +95,8 @@ object Main {
def parameter: T1RocketTileParameter = generator.parameter
}

implicit def ipConfig: ParserForClass[IPConfig] = ParserForClass[IPConfig]
implicit def rocketConfig: ParserForClass[RocketConfig] = ParserForClass[RocketConfig]
implicit def ipConfig: ParserForClass[IPConfig] = ParserForClass[IPConfig]
implicit def rocketConfig: ParserForClass[RocketConfig] = ParserForClass[RocketConfig]
implicit def t1RocketConfig: ParserForClass[T1RocketConfig] = ParserForClass[T1RocketConfig]

@main def ip(elaborateConfig: ElaborateConfig, ipConfig: IPConfig): Unit =
Expand Down
10 changes: 4 additions & 6 deletions elaborator/src/rocketv/BTB.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ object BTB extends Elaborator {
@arg(name = "nEntries") nEntries: Int,
@arg(name = "counterLength") counterLength: Int,
@arg(name = "historyLength") historyLength: Int,
@arg(name = "historyBits") historyBits: Int) {
@arg(name = "historyBits") historyBits: Int) {
def convert: BHTParameter = BHTParameter(
nEntries,
counterLength,
Expand All @@ -39,8 +39,7 @@ object BTB extends Elaborator {
@arg(name = "bht-counterLength") counterLength: Option[Int],
@arg(name = "bht-historyLength") historyLength: Option[Int],
@arg(name = "bht-historyBits") historyBits: Option[Int],
@arg(name = "fetchWidth") fetchWidth: Int,
) {
@arg(name = "fetchWidth") fetchWidth: Int) {
def convert: BTBParameter = BTBParameter(
useAsyncReset,
fetchBytes,
Expand All @@ -58,9 +57,8 @@ object BTB extends Elaborator {
.lazyZip(counterLength)
.lazyZip(historyLength)
.lazyZip(historyBits))
.map {
case (nEntries, counterLength, historyLength, historyBits) =>
BHTParameter(nEntries, counterLength, historyLength, historyBits)
.map { case (nEntries, counterLength, historyLength, historyBits) =>
BHTParameter(nEntries, counterLength, historyLength, historyBits)
}
.headOption
)
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/CSR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ object CSR extends Elaborator {
@arg(name = "usingAtomics") usingAtomics: Boolean,
@arg(name = "usingDebug") usingDebug: Boolean,
@arg(name = "usingMulDiv") usingMulDiv: Boolean,
@arg(name = "usingVector") usingVector: Boolean) {
@arg(name = "usingVector") usingVector: Boolean) {
def convert: CSRParameter = CSRParameter(
useAsyncReset: Boolean,
vLen: Int,
Expand Down
12 changes: 6 additions & 6 deletions elaborator/src/rocketv/DCache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ import org.chipsalliance.t1.elaborator.Elaborator

object DCache extends Elaborator {
implicit object BitSetRead extends TokensReader.Simple[BitSet] {
def shortName = "bitset"
def shortName = "bitset"
def read(strs: Seq[String]) = {
Right(
strs.head
Expand All @@ -19,13 +19,13 @@ object DCache extends Elaborator {
if (opt.contains("-")) {
val range = opt.split("-")
require(range.size == 2)
val from = BigInt(range.head, 16)
val to = BigInt(range.last, 16) + 1
val from = BigInt(range.head, 16)
val to = BigInt(range.last, 16) + 1
BitSet.fromRange(from, to - from, range.head.length * 4)
} else if (opt.contains("+")) {
val range = opt.split("\\+")
val range = opt.split("\\+")
require(range.size == 2)
val from = BigInt(range.head, 16)
val from = BigInt(range.head, 16)
val length = BigInt(range.last, 16)
BitSet.fromRange(from, length, range.head.length * 4)
} else {
Expand Down Expand Up @@ -63,7 +63,7 @@ object DCache extends Elaborator {
@arg(name = "logic") logic: BitSet,
@arg(name = "arithmetic") arithmetic: BitSet,
@arg(name = "exec") exec: BitSet,
@arg(name = "sideEffects") sideEffects: BitSet) {
@arg(name = "sideEffects") sideEffects: BitSet) {
def convert: HellaCacheParameter = HellaCacheParameter(
useAsyncReset,
clockGate,
Expand Down
4 changes: 2 additions & 2 deletions elaborator/src/rocketv/Decoder.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@ import org.chipsalliance.t1.elaborator.Elaborator
object Decoder extends Elaborator {
@main
case class DecoderParameterMain(
@arg(name = "instructionSets") instructionSets: Set[String],
@arg(name = "pipelinedMul") pipelinedMul: Boolean,
@arg(name = "instructionSets") instructionSets: Set[String],
@arg(name = "pipelinedMul") pipelinedMul: Boolean,
@arg(name = "fenceIFlushDCache") fenceIFlushDCache: Boolean) {
def convert: DecoderParameter = DecoderParameter(
instructionSets,
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/FPToFP.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ object FPToFP extends Elaborator {
latency: Int,
xLen: Int,
fLen: Int,
minFLen: Int) {
minFLen: Int) {
def convert: FPToFPParameter = FPToFPParameter(
useAsyncReset,
latency,
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/FPToInt.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ object FPToInt extends Elaborator {
@arg(name = "useAsyncReset") useAsyncReset: Boolean,
@arg(name = "xLen") xLen: Int,
@arg(name = "fLen") fLen: Int,
@arg(name = "minFLen") minFLen: Int) {
@arg(name = "minFLen") minFLen: Int) {
def convert: FPToIntParameter = FPToIntParameter(
useAsyncReset,
xLen,
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/FPU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ object FPU extends Elaborator {
@arg(name = "sfmaLatency") sfmaLatency: Int,
@arg(name = "dfmaLatency") dfmaLatency: Int,
@arg(name = "divSqrt") divSqrt: Boolean,
@arg(name = "hartIdLen") hartIdLen: Int) {
@arg(name = "hartIdLen") hartIdLen: Int) {
def convert: FPUParameter = FPUParameter(
useAsyncReset,
useClockGating,
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/FPUFMAPipe.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ object FPUFMAPipe extends Elaborator {
xLen: Int,
fLen: Int,
minFLen: Int,
t: String) {
t: String) {

def convert: FPUFMAPipeParameter = FPUFMAPipeParameter(
useAsyncReset,
Expand Down
17 changes: 8 additions & 9 deletions elaborator/src/rocketv/Frontend.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ import org.chipsalliance.t1.elaborator.Elaborator

object Frontend extends Elaborator {
implicit object BitSetRead extends TokensReader.Simple[BitSet] {
def shortName = "bitset"
def shortName = "bitset"
def read(strs: Seq[String]) = {
Right(
strs.head
Expand All @@ -19,13 +19,13 @@ object Frontend extends Elaborator {
if (opt.contains("-")) {
val range = opt.split("-")
require(range.size == 2)
val from = BigInt(range.head, 16)
val to = BigInt(range.last, 16) + 1
val from = BigInt(range.head, 16)
val to = BigInt(range.last, 16) + 1
BitSet.fromRange(from, to - from, range.head.length * 4)
} else if (opt.contains("+")) {
val range = opt.split("\\+")
val range = opt.split("\\+")
require(range.size == 2)
val from = BigInt(range.head, 16)
val from = BigInt(range.head, 16)
val length = BigInt(range.last, 16)
BitSet.fromRange(from, length, range.head.length * 4)
} else {
Expand Down Expand Up @@ -76,7 +76,7 @@ object Frontend extends Elaborator {
@arg(name = "logic") logic: Seq[BitSet],
@arg(name = "arithmetic") arithmetic: Seq[BitSet],
@arg(name = "exec") exec: Seq[BitSet],
@arg(name = "sideEffects") sideEffects: Seq[BitSet]) {
@arg(name = "sideEffects") sideEffects: Seq[BitSet]) {
def convert: FrontendParameter = FrontendParameter(
useAsyncReset: Boolean,
clockGate: Boolean,
Expand Down Expand Up @@ -107,9 +107,8 @@ object Frontend extends Elaborator {
.lazyZip(bhtCounterLength)
.lazyZip(bhtHistoryLength)
.lazyZip(bhtHistoryBits)
.map {
case (bhtNEntries, bhtCounterLength, bhtHistoryLength, bhtHistoryBits) =>
BHTParameter(bhtNEntries, bhtCounterLength, bhtHistoryLength, bhtHistoryBits)
.map { case (bhtNEntries, bhtCounterLength, bhtHistoryLength, bhtHistoryBits) =>
BHTParameter(bhtNEntries, bhtCounterLength, bhtHistoryLength, bhtHistoryBits)
}
.headOption,
legal.foldLeft(BitSet.empty)(_.union(_)),
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/IBuf.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ object IBuf extends Elaborator {
@arg(name = "vaddrBitsExtended") vaddrBitsExtended: Int,
@arg(name = "bhtHistoryLength") bhtHistoryLength: Option[Int],
@arg(name = "bhtCounterLength") bhtCounterLength: Option[Int],
@arg(name = "fetchWidth") fetchWidth: Int) {
@arg(name = "fetchWidth") fetchWidth: Int) {
def convert: IBufParameter = IBufParameter(
useAsyncReset,
xLen,
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/ICache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ object ICache extends Elaborator {
@arg(name = "blockBytes") blockBytes: Int,
@arg(name = "usingVM") usingVM: Boolean,
@arg(name = "vaddrBits") vaddrBits: Int,
@arg(name = "paddrBits") paddrBits: Int) {
@arg(name = "paddrBits") paddrBits: Int) {
def convert: ICacheParameter = ICacheParameter(
useAsyncReset,
prefetch,
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/IntToFP.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ object IntToFP extends Elaborator {
@arg(name = "latency") latency: Int,
@arg(name = "fLen") fLen: Int,
@arg(name = "xLen") xLen: Int,
@arg(name = "minFLen") minFLen: Int) {
@arg(name = "minFLen") minFLen: Int) {
def convert: IntToFPParameter = IntToFPParameter(
useAsyncReset,
latency,
Expand Down
2 changes: 1 addition & 1 deletion elaborator/src/rocketv/MulAddRecFNPipe.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ object MulAddRecFNPipe extends Elaborator {
@arg(name = "useAsyncReset") useAsyncReset: Boolean,
@arg(name = "latency") latency: Int,
@arg(name = "expWidth") expWidth: Int,
@arg(name = "sigWidth") sigWidth: Int) {
@arg(name = "sigWidth") sigWidth: Int) {
def convert: MulAddRecFNPipeParameter = MulAddRecFNPipeParameter(useAsyncReset, latency, expWidth, sigWidth)
}

Expand Down
6 changes: 3 additions & 3 deletions elaborator/src/rocketv/MulDiv.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -17,15 +17,15 @@ object MulDiv extends Elaborator {
@arg(name = "divEarlyOutGranularity") divEarlyOutGranularity: Int,
@arg(name = "mulUnroll") mulUnroll: Int,
@arg(name = "mulEarlyOut") mulEarlyOut: Boolean,
@arg(name = "instructionSets") instructionSets: Set[String],
@arg(name = "pipelinedMul") pipelinedMul: Boolean,
@arg(name = "instructionSets") instructionSets: Set[String],
@arg(name = "pipelinedMul") pipelinedMul: Boolean,
@arg(name = "fenceIFlushDCache") fenceIFlushDCache: Boolean) {
def decodeParam: DecoderParameter = DecoderParameter(
instructionSets,
pipelinedMul,
fenceIFlushDCache
)
def convert: MulDivParameter = MulDivParameter(
def convert: MulDivParameter = MulDivParameter(
useAsyncReset,
latency,
width,
Expand Down
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