[rtl] add write release for mask unit.

t1/src/T1.scala

@@ -773,7 +773,8 @@ class T1(val parameter: T1Parameter)
     )(
       VecInit(Seq(maskUnit.io.exeResp(index), lsu.vrfWritePort(index))),
       lane.vrfWriteChannel,
-      0
+      0,
+      releaseSource = Some(Seq(maskUnit.io.writeRelease(index), lsu.writeRelease(index)))
     )
     lane.writeFromMask := maskUnit.io.exeResp(index).fire
 

t1/src/lsu/LSU.scala

@@ -168,6 +168,9 @@ class LSU(param: LSUParameter) extends Module {
     )
   )
 
+  @public
+  val writeRelease: Vec[Bool] = IO(Vec(param.laneNumber, Input(Bool())))
+
   @public
   val dataInWriteQueue: Vec[UInt] = IO(Output(Vec(param.laneNumber, UInt((2 * param.chainingSize).W))))
 

t1/src/mask/MaskUnit.scala

@@ -56,6 +56,7 @@ class MaskUnitInterface(parameter: T1Parameter) extends Bundle {
       )
     )
   )
+  val writeRelease:      Vec[Bool]                         = Vec(parameter.laneNumber, Input(Bool()))
   val tokenIO:           Vec[LaneTokenBundle]              = Flipped(Vec(parameter.laneNumber, new LaneTokenBundle))
   val readChannel:       Vec[DecoupledIO[VRFReadRequest]]  = Vec(
     parameter.laneNumber,
@@ -1094,7 +1095,7 @@ class MaskUnit(val parameter: T1Parameter)
     Queue.io(new MaskUnitExeResponse(parameter.laneParam), maskUnitWriteQueueSize)
   }
 
-  writeQueue.zipWithIndex.foreach { case (queue, index) =>
+  val dataNotInShifter: Bool = writeQueue.zipWithIndex.map { case (queue, index) =>
     val readTypeWriteVrf: Bool = waiteStageDeqFire && WillWriteLane(index)
     queue.enq.valid              := maskedWrite.out(index).valid || readTypeWriteVrf
     maskedWrite.out(index).ready := queue.enq.ready
@@ -1117,7 +1118,17 @@ class MaskUnit(val parameter: T1Parameter)
       parameter.laneParam.vrfOffsetBits
     )
     writePort.bits.offset           := queue.deq.bits.writeData.groupCounter
-  }
+
+    val writeTokenSize    = 8
+    val writeTokenWidth   = log2Ceil(writeTokenSize)
+    val writeTokenCounter = RegInit(0.U(writeTokenWidth.W))
+
+    val writeTokenChange = Mux(writePort.fire, 1.U(writeTokenWidth.W), -1.S(writeTokenWidth.W).asUInt)
+    when(writePort.fire ^ io.writeRelease(index)) {
+      writeTokenCounter := writeTokenCounter + writeTokenChange
+    }
+    writeTokenCounter === 0.U
+  }.reduce(_ && _)
   waiteStageDeqReady := writeQueue.zipWithIndex.map { case (queue, index) =>
     !WillWriteLane(index) || queue.enq.ready
   }.reduce(_ && _)
@@ -1126,7 +1137,7 @@ class MaskUnit(val parameter: T1Parameter)
   // todo: token
   val waiteLastRequest: Bool = RegInit(false.B)
   val waitQueueClear:   Bool = RegInit(false.B)
-  val lastReportValid = waitQueueClear && !writeQueue.map(_.deq.valid).reduce(_ || _)
+  val lastReportValid = waitQueueClear && !writeQueue.map(_.deq.valid).reduce(_ || _) && dataNotInShifter
   when(lastReportValid) {
     waitQueueClear   := false.B
     waiteLastRequest := false.B

t1/src/package.scala

@@ -282,7 +282,8 @@ package object rtl {
     sink:           DecoupledIO[T],
     arb:            Int,
     dataAck:        Option[UInt] = None,
-    dataToSource:   Option[Seq[ValidIO[UInt]]] = None
+    dataToSource:   Option[Seq[ValidIO[UInt]]] = None,
+    releaseSource:  Option[Seq[Bool]] = None
   ): Unit = {
     val sinkVec: Vec[DecoupledIO[T]] = VecInit(sourceVec.zipWithIndex.map { case (source, index) =>
       val sinkWire: DecoupledIO[T] = Wire(Decoupled(chiselTypeOf(source.bits)))
@@ -303,6 +304,12 @@ package object rtl {
         connectWithShifter(latencyVec(index))(accessDataSource, sourceData)
       }
     }
+    releaseSource.foreach { sourceVec =>
+      sourceVec.zipWithIndex.foreach { case (release, index) =>
+        val sinkRequest = sinkVec(index)
+        release := Pipe(sinkRequest.fire, 0.U.asTypeOf(new EmptyBundle), latencyVec(index)).valid
+      }
+    }
   }
 
   def instantiateVFU(