fix errors of unsign ext

chipsalliance · Aug 5, 2024 · 75516f4 · 75516f4
1 parent b7d4b7a
commit 75516f4
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Showing 3 changed files with 40 additions and 14 deletions.
diff --git a/t1/src/LaneZvbb.scala b/t1/src/LaneZvbb.scala
@@ -25,6 +25,7 @@ class LaneZvbbRequest(datapathWidth: Int) extends VFUPipeBundle {
   val src    = Vec(3, UInt(datapathWidth.W))
   val opcode = UInt(4.W)
   val vSew   = UInt(2.W)
+  val shifterSize = UInt(log2Ceil(datapathWidth).W)
 }
 
 class LaneZvbbResponse(datapathWidth: Int)  extends VFUPipeBundle {
@@ -113,20 +114,13 @@ class LaneZvbb(val parameter: LaneZvbbParam)
     zvbbROR32,
   ))
 
-  // val zvbbSLL64_32 = ((0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0)).asUInt(63, 0)
-  // val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(31, 0) ##
-  //                    ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(31, 0)
-  // val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(15, 0) ##
-  //                   ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(15, 0) ##
-  //                   ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(15, 0) ##
-  //                   ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(15, 0)
-  val zvbbSLL64_32 = ((0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0)).asUInt(31, 0)
-  val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(15, 0) ##
-                     ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(15, 0)
-  val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(7, 0) ##
-                    ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(7, 0) ##
-                    ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(7, 0) ##
-                    ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(7, 0)
+  val zvbbSLL64_32 = ((0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(4, 0)).asUInt(31, 0)
+  val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(3, 0)).asUInt(15, 0) ##
+                     ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(3, 0)).asUInt(15, 0)
+  val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(2, 0)).asUInt(7, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(2, 0)).asUInt(7, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(2, 0)).asUInt(7, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(2, 0)).asUInt(7, 0)
   val zvbbSLL64 = Mux1H(vSew, Seq(
     zvbbSLL64_8,
     zvbbSLL64_16,

diff --git a/t1/src/decoder/attribute/isUnsigned0.scala b/t1/src/decoder/attribute/isUnsigned0.scala
@@ -130,6 +130,22 @@ object isUnsigned0 {
       "vzext.vf2",
       "vzext.vf4",
       "vzext.vf8",
+      // rv_zvbb
+      "vandn.vv",
+      "vandn.vx",
+      "vbrev.v",
+      "vbrev8.v",
+      "vrev8.v",
+      "vclz.v",
+      "vctz.v",
+      "vrol.vv",
+      "vrol.vx",
+      "vror.vv",
+      "vror.vx",
+      "vror.vi",
+      "vwsll.vv",
+      "vwsll.vx",
+      "vwsll.vi",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/isUnsigned1.scala b/t1/src/decoder/attribute/isUnsigned1.scala
@@ -102,6 +102,22 @@ object isUnsigned1 {
       "vzext.vf2",
       "vzext.vf4",
       "vzext.vf8",
+      // rv_zvbb
+      "vandn.vv",
+      "vandn.vx",
+      "vbrev.v",
+      "vbrev8.v",
+      "vrev8.v",
+      "vclz.v",
+      "vctz.v",
+      "vrol.vv",
+      "vrol.vx",
+      "vror.vv",
+      "vror.vx",
+      "vror.vi",
+      "vwsll.vv",
+      "vwsll.vx",
+      "vwsll.vi",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }