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add new pockerman and fix errors
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Lucas-Wye committed Jul 12, 2024
1 parent ce3e5cd commit 6eccbc7
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73 changes: 73 additions & 0 deletions configgen/src/Main.scala
Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,79 @@ object Main {
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
vrfBankSize = 1,
vrfRamType = RamType.p0rwp1rw,
vfuInstantiateParameter = VFUInstantiateParameter(
slotCount = 4,
logicModuleParameters = Seq(
(SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3))
),
aluModuleParameters = Seq(
(SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)),
(SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)),
(SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)),
(SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3))
),
shifterModuleParameters = Seq(
(SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3))
),
mulModuleParameters = Seq(
(SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3))
),
divModuleParameters = Seq(),
divfpModuleParameters =
Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))),
otherModuleParameters =
Seq((
SerializableModuleGenerator(
classOf[OtherUnit],
OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1)
),
Seq(0, 1, 2, 3))),
floatModuleParameters =
Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))),
zvbbModuleParameters = Seq()
)
)
if (doEmit) param.emit(targetFile)
param
}

// DLEN256 VLEN256; FP; VRF p0rw,p1rw bank1; LSU bank8 beatbyte 8; Zvbb
@main def psyduck(
@arg(name = "target-file", short = 't') targetFile: os.Path,
@arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true
): T1Parameter = {
val vLen = 512
val dLen = 256
val param = T1Parameter(
vLen,
dLen,
extensions = Seq("Zve32f", "Zvbb"),
t1customInstructions = Nil,
lsuBankParameters =
// scalar bank 0-1G
Seq(
BitSet(BitPat("b00??????????????????????????????"))
).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++
// ddr bank 1G-3G 512M/bank
Seq(
BitSet(BitPat("b01???????????????????????00?????"), BitPat("b10???????????????????????00?????")),
BitSet(BitPat("b01???????????????????????01?????"), BitPat("b10???????????????????????01?????")),
BitSet(BitPat("b01???????????????????????10?????"), BitPat("b10???????????????????????10?????")),
BitSet(BitPat("b01???????????????????????11?????"), BitPat("b10???????????????????????11?????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 8, false) } ++
// sRam bank 3G+ 256K/bank, 8banks
Seq(
BitSet(BitPat("b11000000000?????????????000?????")),
BitSet(BitPat("b11000000000?????????????001?????")),
BitSet(BitPat("b11000000000?????????????010?????")),
BitSet(BitPat("b11000000000?????????????011?????")),
BitSet(BitPat("b11000000000?????????????100?????")),
BitSet(BitPat("b11000000000?????????????101?????")),
BitSet(BitPat("b11000000000?????????????110?????")),
BitSet(BitPat("b11000000000?????????????111?????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
vrfBankSize = 1,
vrfRamType = RamType.p0rwp1rw,
vfuInstantiateParameter = VFUInstantiateParameter(
slotCount = 4,
logicModuleParameters = Seq(
Expand Down
19 changes: 5 additions & 14 deletions t1/src/LaneZvbb.scala
Original file line number Diff line number Diff line change
Expand Up @@ -38,20 +38,11 @@ class LaneZvbb(val parameter: LaneZvbbParam)

val zvbbSrc: UInt = request.src(0) // vs2
val zvbbRs: UInt = request.src(1) // vs1 or rs1
val zvbbBRev = UInt(parameter.datapathWidth.W) // element's bit reverse
for (i <- 0 until parameter.datapathWidth) {
zvbbBRev:= zvbbBRev ## zvbbSrc(i)
}
val zvbbBRev8 = UInt(parameter.datapathWidth.W) // byte's bit reverse
for (i <- 0 until parameter.datapathWidth/8) {
for (j <- 0 until 8) {
zvbbBRev8 := zvbbBRev8 ## zvbbSrc(i * 8 + j)
}
}
val zvbbRev8 = UInt(parameter.datapathWidth.W) // element's byte reverse
for (i <- 0 until parameter.datapathWidth/8) {
zvbbRev8:= zvbbRev8 ## zvbbSrc(parameter.datapathWidth - i * 8 - 1, parameter.datapathWidth - i * 8 - 1 - 8)
}

val zvbbBRev = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.reverse).asUInt // element's bit reverse
val zvbbBRev8 = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.grouped(8).map(s => VecInit(s.reverse)).toSeq).asUInt // byte's bit reverse
val zvbbRev8 = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.grouped(8).map(s => VecInit(s)).toSeq.reverse).asUInt // element's byte reverse

val zvbbCLZ = UInt(parameter.datapathWidth.W)
for (i <- 0 until parameter.datapathWidth) {
when(zvbbSrc(parameter.datapathWidth-i-1) === 1.U) {
Expand Down
2 changes: 1 addition & 1 deletion t1/src/T1.scala
Original file line number Diff line number Diff line change
Expand Up @@ -135,7 +135,7 @@ case class T1Parameter(
}
}

require(extensions.forall(Seq("Zve32x", "Zve32f").contains), "unsupported extension.")
require(extensions.forall(Seq("Zve32x", "Zve32f", "Zvbb").contains), "unsupported extension.")
// TODO: require bank not overlap
/** xLen of T1, we currently only support 32. */
val xLen: Int = 32
Expand Down
28 changes: 11 additions & 17 deletions t1/src/decoder/Decoder.scala
Original file line number Diff line number Diff line change
Expand Up @@ -40,10 +40,6 @@ trait T1fpExecutionTypeUopField extends T1DecodeFiled[UInt] with FieldName {
def chiselType: UInt = UInt(2.W)
}

trait T1zvbbExecutionTypeUopField extends T1DecodeFiled[UInt] with FieldName {
def chiselType: UInt = UInt(4.W)
}

object Decoder {
object logic extends BoolField {
override def getTriState(pattern: T1DecodePattern): TriState = pattern.isLogic.value
Expand Down Expand Up @@ -336,6 +332,17 @@ object Decoder {
case _: zeroUop0.type => BitPat("b0000")
case _ => BitPat.dontCare(4)
}
case zvbbCase: ZvbbUOPType =>
zvbbCase match {
case _: zvbbUop0.type => BitPat("b0000")
case _: zvbbUop1.type => BitPat("b0001")
case _: zvbbUop2.type => BitPat("b0010")
case _: zvbbUop3.type => BitPat("b0011")
case _: zvbbUop4.type => BitPat("b0100")
case _: zvbbUop5.type => BitPat("b0101")
case _: zvbbUop6.type => BitPat("b0110")
case _ => BitPat.dontCare(4)
}
case _ => BitPat.dontCare(4)
}
}
Expand All @@ -349,18 +356,6 @@ object Decoder {
}
}

object zvbbExecutionType extends T1zvbbExecutionTypeUopField {
override def genTable(pattern: T1DecodePattern): BitPat = pattern.zvbbExecutionType match {
case ZvbbExecutionType.Brev => BitPat("b0000")
case ZvbbExecutionType.Brev8 => BitPat("b0001")
case ZvbbExecutionType.Rev8 => BitPat("b0010")
case ZvbbExecutionType.CLZ => BitPat("b0011")
case ZvbbExecutionType.CTZ => BitPat("b0100")
case ZvbbExecutionType.ROL => BitPat("b0101")
case ZvbbExecutionType.ROR => BitPat("b0110")
case ZvbbExecutionType.Nil => BitPat.dontCare(4)
}
}

def allFields(param: DecoderParam): Seq[T1DecodeFiled[_ >: Bool <: UInt]] = Seq(
logic,
Expand Down Expand Up @@ -424,7 +419,6 @@ object Decoder {
if (param.zvbbEnable)
Seq(
zvbb,
zvbbExecutionType,
)
else Seq()
}
Expand Down
1 change: 0 additions & 1 deletion t1/src/decoder/T1DecodePattern.scala
Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,6 @@ case class T1DecodePattern(instruction: Instruction, param: DecoderParam) extend
def fpExecutionType: FpExecutionType.Type = attribute.FpExecutionType(this)
def topUop: TopUop = attribute.TopUop(this)
def decoderUop: DecoderUop = attribute.DecoderUop(this)
def zvbbExecutionType: ZvbbExecutionType.Type = attribute.ZvbbExecutionType(this)

private def documentation: String = InstructionDocumentation(instruction, param).toString

Expand Down
17 changes: 0 additions & 17 deletions t1/src/decoder/attribute/isScheduler.scala
Original file line number Diff line number Diff line change
Expand Up @@ -260,23 +260,6 @@ object isScheduler {
"vxor.vi",
"vxor.vv",
"vxor.vx",
// rv_zvbb
"vandn.vv",
"vandn.vx",
"vbrev.v",
"vbrev8.v",
"vrev8.v",
"vclz.v",
"vctz.v",
"vcpop.v",
"vrol.vv",
"vrol.vx",
"vror.vv",
"vror.vx",
"vror.vi",
"vwsll.vv",
"vwsll.vx",
"vwsll.vi",
)
allMatched.contains(t1DecodePattern.instruction.name)
}
Expand Down
6 changes: 0 additions & 6 deletions t1/src/decoder/attribute/isVtype.scala
Original file line number Diff line number Diff line change
Expand Up @@ -183,15 +183,9 @@ object isVtype {
"vzext.vf8",
// rv_zvbb
"vandn.vv",
"vandn.vx",
"vrol.vv",
"vrol.vx",
"vror.vv",
"vror.vx",
"vror.vi",
"vwsll.vv",
"vwsll.vx",
"vwsll.vi",
)
allMatched.contains(t1DecodePattern.instruction.name)
}
Expand Down
3 changes: 2 additions & 1 deletion t1/src/decoder/attribute/uop.scala
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,8 @@ object DecoderUop {
isLogic.y(t1DecodePattern) -> LogicUop(t1DecodePattern),
isShift.y(t1DecodePattern) -> ShiftUop(t1DecodePattern),
isOther.y(t1DecodePattern) -> OtherUop(t1DecodePattern),
isZero.y(t1DecodePattern) -> ZeroUOP(t1DecodePattern)
isZero.y(t1DecodePattern) -> ZeroUOP(t1DecodePattern),
isZvbb.y(t1DecodePattern) -> ZvbbUOP(t1DecodePattern),
).collectFirst {
case (fn, tpe) if fn => DecoderUop(tpe)
}
Expand Down
88 changes: 0 additions & 88 deletions t1/src/decoder/attribute/zvbbExecutionType.scala

This file was deleted.

76 changes: 76 additions & 0 deletions t1/src/decoder/attribute/zvbbUop.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,76 @@
// SPDX-License-Identifier: Apache-2.0
// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]>

package org.chipsalliance.t1.rtl.decoder.attribute

import org.chipsalliance.t1.rtl.decoder.T1DecodePattern

trait ZvbbUOPType extends Uop
object zvbbUop0 extends ZvbbUOPType
object zvbbUop1 extends ZvbbUOPType
object zvbbUop2 extends ZvbbUOPType
object zvbbUop3 extends ZvbbUOPType
object zvbbUop4 extends ZvbbUOPType
object zvbbUop5 extends ZvbbUOPType
object zvbbUop6 extends ZvbbUOPType

object ZvbbUOP {
def apply(t1DecodePattern: T1DecodePattern): Uop = {
Seq(
t0 _ -> zvbbUop0,
t1 _ -> zvbbUop1,
t2 _ -> zvbbUop2,
t3 _ -> zvbbUop3,
t4 _ -> zvbbUop4,
t5 _ -> zvbbUop5,
t6 _ -> zvbbUop6,
).collectFirst {
case (fn, tpe) if fn(t1DecodePattern) => tpe
}.getOrElse(UopDC)
}
def t0(t1DecodePattern: T1DecodePattern): Boolean = {
val allMatched: Seq[String] = Seq(
"vbrev.v"
)
allMatched.contains(t1DecodePattern.instruction.name)
}
def t1(t1DecodePattern: T1DecodePattern): Boolean = {
val allMatched: Seq[String] = Seq(
"vbrev8.v"
)
allMatched.contains(t1DecodePattern.instruction.name)
}
def t2(t1DecodePattern: T1DecodePattern): Boolean = {
val allMatched: Seq[String] = Seq(
"vrev8.v"
)
allMatched.contains(t1DecodePattern.instruction.name)
}
def t3(t1DecodePattern: T1DecodePattern): Boolean = {
val allMatched: Seq[String] = Seq(
"vclz.v"
)
allMatched.contains(t1DecodePattern.instruction.name)
}
def t4(t1DecodePattern: T1DecodePattern): Boolean = {
val allMatched: Seq[String] = Seq(
"vctz.v"
)
allMatched.contains(t1DecodePattern.instruction.name)
}
def t5(t1DecodePattern: T1DecodePattern): Boolean = {
val allMatched: Seq[String] = Seq(
"vrol.vv",
"vrol.vx",
)
allMatched.contains(t1DecodePattern.instruction.name)
}
def t6(t1DecodePattern: T1DecodePattern): Boolean = {
val allMatched: Seq[String] = Seq(
"vror.vv",
"vror.vx",
"vror.vi",
)
allMatched.contains(t1DecodePattern.instruction.name)
}
}

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