[rtl] switch to Blackbox-base SRAM

Signed-off-by: unlsycn <[email protected]>
chipsalliance · Dec 9, 2024 · 6bbb5c3 · 6bbb5c3
1 parent 4838af2
commit 6bbb5c3
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Showing 9 changed files with 22 additions and 22 deletions.
diff --git a/elaborator/src/rocketv/Frontend.scala b/elaborator/src/rocketv/Frontend.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.rocketv.{BHTParameter, Frontend, FrontendParameter}
 
@@ -137,7 +137,7 @@ object Frontend extends SerializableModuleElaborator {
   implicit def FrontendParameterMainParser: ParserForClass[FrontendParameterMain] =
     ParserForClass[FrontendParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =

diff --git a/elaborator/src/rocketv/ICache.scala b/elaborator/src/rocketv/ICache.scala
@@ -3,7 +3,7 @@
 package org.chipsalliance.t1.elaborator.rocketv
 
 import chisel3.experimental.util.SerializableModuleElaborator
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.rocketv.{ICache, ICacheParameter}
 
@@ -42,7 +42,7 @@ object ICache extends SerializableModuleElaborator {
 
   implicit def ICacheParameterMainParser: ParserForClass[ICacheParameterMain] = ParserForClass[ICacheParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =

diff --git a/elaborator/src/rocketv/RocketTile.scala b/elaborator/src/rocketv/RocketTile.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.rocketv.{BHTParameter, RocketTile, RocketTileParameter}
 
@@ -191,7 +191,7 @@ object RocketTile extends SerializableModuleElaborator {
   implicit def RocketTileParameterMainParser: ParserForClass[RocketTileParameterMain] =
     ParserForClass[RocketTileParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =

diff --git a/elaborator/src/t1/T1.scala b/elaborator/src/t1/T1.scala
@@ -3,7 +3,7 @@
 package org.chipsalliance.t1.elaborator.t1
 
 import chisel3.experimental.util.SerializableModuleElaborator
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.t1.rtl.vrf.RamType
 import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
@@ -59,7 +59,7 @@ object T1 extends SerializableModuleElaborator {
 
   implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =

diff --git a/elaborator/src/t1emu/TestBench.scala b/elaborator/src/t1emu/TestBench.scala
@@ -3,7 +3,7 @@
 package org.chipsalliance.t1.elaborator.t1emu
 
 import chisel3.experimental.util.SerializableModuleElaborator
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.t1.rtl.vrf.RamType
 import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
@@ -60,7 +60,7 @@ object TestBench extends SerializableModuleElaborator {
 
   implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =

diff --git a/elaborator/src/t1rocket/T1RocketTile.scala b/elaborator/src/t1rocket/T1RocketTile.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.t1.rtl.VFUInstantiateParameter
 import org.chipsalliance.t1.rtl.vrf.RamType
@@ -112,7 +112,7 @@ object T1RocketTile extends SerializableModuleElaborator {
   implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
     ParserForClass[T1RocketTileParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =

diff --git a/elaborator/src/t1rocketemu/TestBench.scala b/elaborator/src/t1rocketemu/TestBench.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketemu
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.t1.rtl.VFUInstantiateParameter
 import org.chipsalliance.t1.rtl.vrf.RamType
@@ -113,7 +113,7 @@ object TestBench extends SerializableModuleElaborator {
   implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
     ParserForClass[T1RocketTileParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =

diff --git a/nix/t1/dependencies/_sources/generated.json b/nix/t1/dependencies/_sources/generated.json
@@ -41,7 +41,7 @@
     },
     "chisel": {
         "cargoLocks": null,
-        "date": "2024-12-07",
+        "date": "2024-12-08",
         "extract": null,
         "name": "chisel",
         "passthru": null,
@@ -53,11 +53,11 @@
             "name": null,
             "owner": "chipsalliance",
             "repo": "chisel",
-            "rev": "5871a65195c7ad96edb9c58dd94cddd942815dfb",
-            "sha256": "sha256-0xh7Xg2vi+GmoTQHNFJPQ5MP7r1UDmiGcJUI45YE16A=",
+            "rev": "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f",
+            "sha256": "sha256-s6y4jlTvh4q6mWXCGzxxUtFaekZ9BDT9FhrSqvtWnwE=",
             "type": "github"
         },
-        "version": "5871a65195c7ad96edb9c58dd94cddd942815dfb"
+        "version": "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f"
     },
     "chisel-interface": {
         "cargoLocks": null,

diff --git a/nix/t1/dependencies/_sources/generated.nix b/nix/t1/dependencies/_sources/generated.nix
@@ -27,15 +27,15 @@
   };
   chisel = {
     pname = "chisel";
-    version = "5871a65195c7ad96edb9c58dd94cddd942815dfb";
+    version = "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f";
     src = fetchFromGitHub {
       owner = "chipsalliance";
       repo = "chisel";
-      rev = "5871a65195c7ad96edb9c58dd94cddd942815dfb";
+      rev = "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f";
       fetchSubmodules = false;
-      sha256 = "sha256-0xh7Xg2vi+GmoTQHNFJPQ5MP7r1UDmiGcJUI45YE16A=";
+      sha256 = "sha256-s6y4jlTvh4q6mWXCGzxxUtFaekZ9BDT9FhrSqvtWnwE=";
     };
-    date = "2024-12-07";
+    date = "2024-12-08";
   };
   chisel-interface = {
     pname = "chisel-interface";