[rtl] Check writes before arbitration.

chipsalliance · May 16, 2024 · 68db48f · 68db48f
1 parent 527900a
commit 68db48f
Showing 1 changed file with 25 additions and 3 deletions.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -367,6 +367,12 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   vrfWriteArbiter(parameter.chainingSize).bits := topWriteQueue.bits
   topWriteQueue.ready := vrfWriteArbiter(parameter.chainingSize).ready
 
+  val allVrfWriteAfterCheck: Seq[VRFWriteRequest] = Seq.tabulate(parameter.chainingSize + 3) { i =>
+    RegInit(0.U.asTypeOf(vrfWriteArbiter.head.bits))
+  }
+  val afterCheckValid: Vec[Bool] = VecInit(Seq.tabulate(parameter.chainingSize + 3) { _ => RegInit(false.B)})
+  val afterCheckDequeueReady: Vec[Bool] = Wire(Vec(parameter.chainingSize + 3, Bool()))
+
   /** for each slot, assert when it is asking [[T1]] to change mask */
   val slotMaskRequestVec: Vec[ValidIO[UInt]] = Wire(
     Vec(
@@ -894,13 +900,29 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     vrf.readCheck.zip(readCheckRequestVec).foreach{case (sink, source) => sink := source}
     readCheckResult.zip(vrf.readCheckResult).foreach{case (sink, source) => sink := source}
 
+    allVrfWriteAfterCheck.zipWithIndex.foreach { case (req, i) =>
+      val check = vrf.writeAllow(i)
+      val enqReady = check && (!afterCheckValid(i) || afterCheckDequeueReady(i))
+      val enqFire = enqReady && allVrfWrite(i).valid
+      allVrfWrite(i).ready := enqReady
+      when(enqFire) {
+        req := allVrfWrite(i).bits
+      }
+      val deqFire = afterCheckDequeueReady(i) && afterCheckValid(i)
+      when(deqFire ^ enqFire) {
+        afterCheckValid(i) := enqFire
+      }
+    }
+
     // Arbiter
-    val writeSelect: UInt = ffo(checkResult & VecInit(allVrfWrite.map(_.valid)).asUInt)
-    allVrfWrite.zipWithIndex.foreach{ case (p, i) => p.ready := writeSelect(i) && queueBeforeMaskWrite.io.enq.ready }
+    val writeSelect: UInt = ffo(afterCheckValid.asUInt)
+    afterCheckDequeueReady.zipWithIndex.foreach { case (p, i) =>
+      p := writeSelect(i) && queueBeforeMaskWrite.io.enq.ready
+    }
 
     maskedWriteUnit.enqueue <> queueBeforeMaskWrite.io.deq
     queueBeforeMaskWrite.io.enq.valid := writeSelect.orR
-    queueBeforeMaskWrite.io.enq.bits := Mux1H(writeSelect, allVrfWrite.map(_.bits))
+    queueBeforeMaskWrite.io.enq.bits := Mux1H(writeSelect, allVrfWriteAfterCheck)
 
     vrf.write <> maskedWriteUnit.dequeue
     readBeforeMaskedWrite <> maskedWriteUnit.vrfReadRequest