Skip to content

Commit

Permalink
[rtl] use piped decode result when connect vfu.
Browse files Browse the repository at this point in the history
  • Loading branch information
qinjun-li committed May 30, 2024
1 parent 9a7ed06 commit 66a07b4
Show file tree
Hide file tree
Showing 2 changed files with 8 additions and 7 deletions.
12 changes: 5 additions & 7 deletions t1/src/Lane.scala
Original file line number Diff line number Diff line change
Expand Up @@ -466,6 +466,9 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
/** request from slot to vfu. */
val requestVec: Vec[SlotRequestToVFU] = Wire(Vec(parameter.chainingSize, new SlotRequestToVFU(parameter)))

/** decode message for [[requestVec]]. */
val executeDecodeVec: Vec[DecodeBundle] = Wire(Vec(parameter.chainingSize, Decoder.bundle(parameter.fpuEnable)))

/** response from vfu to slot. */
val responseVec: Vec[ValidIO[VFUResponseToSlot]] = Wire(Vec(parameter.chainingSize, Valid(new VFUResponseToSlot(parameter))))

Expand Down Expand Up @@ -726,6 +729,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[

// executionUnit <> vfu
requestVec(index) := executionUnit.vfuRequest.bits
executeDecodeVec(index) := executionUnit.executeDecode
executeEnqueueValid(index) := executionUnit.vfuRequest.valid
executionUnit.vfuRequest.ready := executeEnqueueFire(index)
executionUnit.dataResponse := responseVec(index)
Expand Down Expand Up @@ -820,17 +824,11 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
assert(queue.io.enq.ready || !port.enq.valid)
port.enqRelease := queue.io.deq.fire
}
// convert data types


// VFU
// TODO: reuse logic, adder, multiplier datapath
val decodeResultVec: Seq[DecodeBundle] = slotControl.map(_.laneRequest.decodeResult)

val vfus: Seq[Instance[VFUModule]] = instantiateVFU(parameter.vfuInstantiateParameter)(
requestVec,
executeEnqueueValid,
decodeResultVec,
executeDecodeVec,
executeEnqueueFire,
responseVec,
executeOccupied,
Expand Down
3 changes: 3 additions & 0 deletions t1/src/laneStage/LaneExecutionBridge.scala
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,8 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
val ffoByOtherLanes: Bool = IO(Input(Bool()))
@public
val selfCompleted: Bool = IO(Input(Bool()))
@public
val executeDecode: DecodeBundle = IO(Output(Decoder.bundle(parameter.fpuEnable)))

val executionRecord: ExecutionUnitRecord = RegInit(0.U.asTypeOf(new ExecutionUnitRecord(parameter)(isLastSlot)))
val executionRecordValid = RegInit(false.B)
Expand Down Expand Up @@ -293,6 +295,7 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd

// from float csr
vfuRequest.bits.roundingMode.foreach(_ := executionRecord.csr.vxrm)
executeDecode := executionRecord.decodeResult

vfuRequest.valid := (if (isLastSlot) {
(executionRecordValid || sendFoldReduce.get) && (responseFinish || !executionRecord.decodeResult(Decoder.red))
Expand Down

0 comments on commit 66a07b4

Please sign in to comment.