fix

chipsalliance · Aug 13, 2024 · 65296df · 65296df
1 parent cdb458a
commit 65296df
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/rocketv/src/CSR.scala b/rocketv/src/CSR.scala
@@ -866,7 +866,7 @@ class CSR(val parameter: CSRParameter)
     sgeip_mask.sgeip := true.B
     read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt)
   }
-  if (true) {
+  if (usingSupervisor) {
     val read_sie = reg_mie & sie_mask
     val read_sip = read_mip & sie_mask
     val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus))