[ci] update test case cycle data

chipsalliance · Jun 17, 2024 · 6247e55 · 6247e55
1 parent 02d5496
commit 6247e55
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Showing 3 changed files with 25 additions and 25 deletions.
diff --git a/.github/cases/blastoise/default.json b/.github/cases/blastoise/default.json
@@ -1,7 +1,7 @@
 {
   "mlir.rvv_vp_intrinsic_add": 386,
-  "mlir.rvv_vp_intrinsic_add_scalable": 581,
-  "mlir.hello": 94,
+  "mlir.rvv_vp_intrinsic_add_scalable": 567,
+  "mlir.hello": 91,
   "mlir.stripmining": 26732,
   "asm.mmm": 92609,
   "asm.smoke": 5017,
@@ -499,15 +499,15 @@
   "codegen.vfredusum_vs": 100812,
   "codegen.vfredmax_vs": 100812,
   "codegen.vfredmin_vs": 100812,
-  "rvv_bench.ascii_to_utf16": 1544388,
-  "rvv_bench.ascii_to_utf32": 674573,
+  "rvv_bench.ascii_to_utf16": 1544483,
+  "rvv_bench.ascii_to_utf32": 674689,
   "rvv_bench.byteswap": 3364202,
   "rvv_bench.chacha20": 0,
   "rvv_bench.mandelbrot": 4055251,
-  "rvv_bench.memcpy": 1485024,
-  "rvv_bench.memset": 373911,
-  "rvv_bench.mergelines": 3275863,
+  "rvv_bench.memcpy": 1717636,
+  "rvv_bench.memset": 373712,
+  "rvv_bench.mergelines": 3310606,
   "rvv_bench.poly1305": 0,
-  "rvv_bench.strlen": 876331,
-  "rvv_bench.utf8_count": 6320514
+  "rvv_bench.strlen": 876017,
+  "rvv_bench.utf8_count": 6320478
 }
diff --git a/.github/cases/machamp/default.json b/.github/cases/machamp/default.json
@@ -1,6 +1,6 @@
 {
   "mlir.rvv_vp_intrinsic_add": 410,
-  "mlir.rvv_vp_intrinsic_add_scalable": 626,
+  "mlir.rvv_vp_intrinsic_add_scalable": 596,
   "mlir.hello": 95,
   "mlir.stripmining": 14447,
   "asm.mmm": 91473,
@@ -435,14 +435,14 @@
   "codegen.vxor_vx": 74636,
   "codegen.vzext_vf2": 39984,
   "codegen.vzext_vf4": 6585,
-  "rvv_bench.ascii_to_utf16": 1464354,
-  "rvv_bench.ascii_to_utf32": 629517,
+  "rvv_bench.ascii_to_utf16": 1464627,
+  "rvv_bench.ascii_to_utf32": 629781,
   "rvv_bench.byteswap": 3294942,
   "rvv_bench.chacha20": 0,
-  "rvv_bench.memcpy": 1576831,
-  "rvv_bench.memset": 287462,
-  "rvv_bench.mergelines": 3092453,
+  "rvv_bench.memcpy": 1822850,
+  "rvv_bench.memset": 287111,
+  "rvv_bench.mergelines": 3128950,
   "rvv_bench.poly1305": 0,
-  "rvv_bench.strlen": 711050,
-  "rvv_bench.utf8_count": 5726377
+  "rvv_bench.strlen": 711138,
+  "rvv_bench.utf8_count": 5726147
 }
diff --git a/.github/cases/sandslash/default.json b/.github/cases/sandslash/default.json
@@ -1,6 +1,6 @@
 {
   "mlir.rvv_vp_intrinsic_add": 432,
-  "mlir.rvv_vp_intrinsic_add_scalable": 734,
+  "mlir.rvv_vp_intrinsic_add_scalable": 702,
   "mlir.hello": 105,
   "mlir.stripmining": 15253,
   "asm.mmm": 91490,
@@ -435,14 +435,14 @@
   "codegen.vxor_vx": 523658,
   "codegen.vzext_vf2": 167305,
   "codegen.vzext_vf4": 26795,
-  "rvv_bench.ascii_to_utf16": 1392509,
-  "rvv_bench.ascii_to_utf32": 594028,
+  "rvv_bench.ascii_to_utf16": 1392595,
+  "rvv_bench.ascii_to_utf32": 594118,
   "rvv_bench.byteswap": 3602804,
   "rvv_bench.chacha20": 0,
-  "rvv_bench.memcpy": 1840029,
-  "rvv_bench.memset": 202628,
-  "rvv_bench.mergelines": 3052758,
+  "rvv_bench.memcpy": 2113707,
+  "rvv_bench.memset": 202519,
+  "rvv_bench.mergelines": 3042492,
   "rvv_bench.poly1305": 0,
-  "rvv_bench.strlen": 720670,
-  "rvv_bench.utf8_count": 4814077
+  "rvv_bench.strlen": 720886,
+  "rvv_bench.utf8_count": 4814154
 }