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[perf] canonicalize code style
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* Use the trait style specification for all monitors
* clang-format all cpp source code

Signed-off-by: Avimitin <[email protected]>
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@Avimitin
Avimitin committed Oct 5, 2023
1 parent d3e317c commit 6103dd4
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Showing 13 changed files with 937 additions and 1,058 deletions.
238 changes: 44 additions & 194 deletions elaborator/src/PerfMonitor.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,97 +14,42 @@ trait IndexedPerfMonitor extends PerfMonitor {
}

trait ValidMonitor extends PerfMonitor {
val valid = dpiIn("valid", Input(Bool()))
val isValid = dpiIn("isValid", Input(Bool()))
}

trait ReadyMonitor extends PerfMonitor {
val ready = dpiIn("ready", Input(Bool()))
val isReady = dpiIn("isReady", Input(Bool()))
}

trait IndexedValidMonitor extends ValidMonitor with IndexedPerfMonitor
trait IndexedReadyMonitor extends ReadyMonitor with IndexedPerfMonitor
trait ReadyAndValidMonitor extends ValidMonitor with ReadyMonitor

/**
* Monitor signals in [[v.LoadUnit]]
*/
class LoadUnitMonitor extends DPIModule {
override val isImport = true;

val clock = dpiTrigger("clock", Input(Bool()))

class LoadUnitMonitor extends PerfMonitor {
val tlPortAIsValid = dpiIn("LoadUnitTlPortAIsValid", Input(Bool()))
val tlPortAIsReady = dpiIn("LoadUnitTlPortAIsReady", Input(Bool()))

val statusIdle = dpiIn("LoadUnitStatusIdle", Input(Bool()))
val statusLast = dpiIn("LoadUnitStatusLast", Input(Bool()))

val writeReadyForLSU = dpiIn("LoadUnitWriteReadyForLSU", Input(Bool()))

override val trigger: String = s"always @(posedge ${clock.name})";
}

/**
* Monitor signals in tilelink port D in [[v.LoadUnit]]
*/
class LoadUnitPortDMonitor extends DPIModule {
override val isImport = true;

val clock = dpiTrigger("clock", Input(Bool()))
class LoadUnitPortDMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

val portDIndex = dpiIn("VRFPortDIndex", Input(UInt(32.W)))
val portDIsValid = dpiIn("VRFPortDIsValid", Input(Bool()))
val portDIsReady = dpiIn("VRFPortDIsReady", Input(Bool()))
class LoadUnitVrfWritePortMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

override val trigger: String = s"always @(posedge ${clock.name})";
class LoadUnitLastCacheLineAckMonitor extends IndexedPerfMonitor {
val isAck = dpiIn("LoadUnitLastCacheLineIsAck", Input(Bool()))
}

/**
* Monitor signals in VRF write port in [[v.LoadUnit]]
*/
class LoadUnitVrfWritePortMonitor extends DPIModule {
override val isImport = true;
class LoadUnitCacheLineDequeueMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor
// End of LoadUnit monitor definition

val clock = dpiTrigger("clock", Input(Bool()))

val index = dpiIn("LoadUnitVrfWritePortIndex", Input(UInt(32.W)))
val isReady = dpiIn("LoadUnitVrfWritePortIsReady", Input(Bool()))
val isValid = dpiIn("LoadUnitVrfWritePortIsValid", Input(Bool()))

override val trigger: String = s"always @(posedge ${clock.name})";
}

/**
* Monitor lastCacheLineAck status [[v.LoadUnit]]
* Monitor signals in [[v.SimpleAccessUnit]]
*/
class LoadUnitLastCacheLineAckMonitor extends DPIModule {
override val isImport = true;

val clock = dpiTrigger("clock", Input(Bool()))

val index = dpiIn("LoadUnitLastCacheLineAckIndex", Input(UInt(32.W)))
val isAck = dpiIn("LoadUnitLastCacheLineIsAck", Input(Bool()))

override val trigger: String = s"always @(posedge ${clock.name})";
}

class LoadUnitCacheLineDequeueMonitor extends DPIModule {
override val isImport = true;

val clock = dpiTrigger("clock", Input(Bool()))

val index = dpiIn("LoadUnitCacheLineDequeueIndex", Input(UInt(32.W)))
val isValid = dpiIn("LoadUnitCacheLineDequeueIsValid", Input(Bool()))
val isReady = dpiIn("LoadUnitCacheLineDequeueIsReady", Input(Bool()))

override val trigger: String = s"always @(posedge ${clock.name})";
}

class SimpleAccessUnitMonitor extends DPIModule {
override val isImport = true;

val clock = dpiTrigger("clock", Input(Bool()))

class SimpleAccessUnitMonitor extends PerfMonitor {
val lsuRequestIsValid = dpiIn("SimpleAccessUnitLSURequestIsValid", Input(Bool()))

val vrfReadDataPortsIsReady = dpiIn("SimpleAccessUnitVRFReadDataPortsIsReady", Input(Bool()))
Expand All @@ -116,190 +61,95 @@ class SimpleAccessUnitMonitor extends DPIModule {
val vrfWritePortIsValid = dpiIn("SimpleAccessUnitVRFWritePortIsValid", Input(Bool()))

val currentLane = dpiIn("SimpleAccessUnitStatusTargetLane", Input(UInt(32.W)))
val statusIsOffsetGroupEnd = dpiIn("SimpleAccessUnitStatusIsOffsetGroupEnd", Input(Bool()))
val statusIsWaitingFirstResponse = dpiIn("SimpleAccessUnitStatusIsWaitingFirstResponse", Input(Bool()))

val s0Fire = dpiIn("SimpleAccessUnitS0Fire", Input(Bool()))
val s1Fire = dpiIn("SimpleAccessUnitS1Fire", Input(Bool()))
val s2Fire = dpiIn("SimpleAccessUnitS2Fire", Input(Bool()))

override val trigger: String = s"always @(posedge ${clock.name})";
}

class SimpleAccessUnitOffsetReadResultMonitor extends DPIModule {
override val isImport = true;

val clock = dpiTrigger("clock", Input(Bool()))

val index = dpiIn("SimpleAccessUnitOffSetReadResultIndex", Input(UInt(32.W)))
val offsetReadResultIsValid = dpiIn("SimpleAccessUnitOffsetReadResultIsValid", Input(Bool()))

override val trigger: String = s"always @(posedge ${clock.name})";
}

class SimpleAccessUnitIndexedInsnOffsetsIsValidMonitor extends DPIModule {
override val isImport = true;
val clock = dpiTrigger("clock", Input(Bool()))
class SimpleAccessUnitOffsetReadResultMonitor extends IndexedPerfMonitor with ValidMonitor

val index = dpiIn("SimpleAccessUnitIndexedInsnOffsetsIndex", Input(UInt(32.W)))
val isValid = dpiIn("SimpleAccessUnitIndexedInsnOffsetsIsValid", Input(Bool()))
class SimpleAccessUnitIndexedInsnOffsetsIsValidMonitor extends IndexedPerfMonitor with ValidMonitor
// End of SimpleAccessUnit monitors definition

override val trigger: String = s"always @(posedge ${clock.name})";
}

class StoreUnitMonitor extends DPIModule {
override val isImport: Boolean = true;
val clock = dpiTrigger("clock", Input(Bool()))
override val trigger: String = s"always @(posedge ${clock.name})";

/**
* Monitor signals in [[v.StoreUnit]]
*/
class StoreUnitMonitor extends PerfMonitor {
val vrfReadyToStore = dpiIn("VrfReadyToStore", Input(Bool()))
val alignedDequeueValid = dpiIn("AlignedDequeueValid", Input(Bool()))
val alignedDequeueReady = dpiIn("AlignedDequeueReady", Input(Bool()))
}

// Monitor tlPortA in [[v.StoreUnit]]
class StoreUnitTlPortAValidMonitor extends DPIModule {
override val isImport: Boolean = true;
val clock = dpiTrigger("clock", Input(Bool()))
override val trigger: String = s"always @(posedge ${clock.name})";

val index = dpiIn("index", Input(UInt(32.W)))
val valid = dpiIn("valid", Input(Bool()))
}

class StoreUnitTlPortAReadyMonitor extends DPIModule {
override val isImport: Boolean = true;
val clock = dpiTrigger("clock", Input(Bool()))
override val trigger: String = s"always @(posedge ${clock.name})";
class StoreUnitAlignedDequeueMonitor extends PerfMonitor with ValidMonitor with ReadyMonitor

val index = dpiIn("index", Input(UInt(32.W)))
val ready = dpiIn("ready", Input(Bool()))
}
class StoreUnitTlPortAMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class StoreUnitVrfReadDataPortValidMonitor extends DPIModule {
override val isImport: Boolean = true;
val clock = dpiTrigger("clock", Input(Bool()))
override val trigger: String = s"always @(posedge ${clock.name})";

val index = dpiIn("index", Input(UInt(32.W)))
val valid = dpiIn("valid", Input(Bool()))
}
class StoreUnitVrfReadDataPortMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class StoreUnitVrfReadDataPortReadyMonitor extends DPIModule {
override val isImport: Boolean = true;
val clock = dpiTrigger("clock", Input(Bool()))
override val trigger: String = s"always @(posedge ${clock.name})";

val index = dpiIn("index", Input(UInt(32.W)))
val ready = dpiIn("ready", Input(Bool()))
}

abstract class LaneMonitor extends PerfMonitor {
val laneIndex = dpiIn("laneIndex", Input(UInt(32.W)))
}

class LaneReadBusPortMonitor extends LaneMonitor {
class LaneReadBusPortMonitor extends IndexedPerfMonitor {
val readBusPortEnqReady = dpiIn("readBusPortEnqReady", Input(Bool()))
val readBusPortEnqValid = dpiIn("readBusPortEnqValid", Input(Bool()))
val readBusPortDeqReady = dpiIn("readBusPortDeqReady", Input(Bool()))
val readBusPortDeqValid = dpiIn("readBusPortDeqValid", Input(Bool()))
}

class LaneWriteBusPortMonitor extends LaneMonitor {
class LaneWriteBusPortMonitor extends IndexedPerfMonitor {
val writeBusPortEnqReady = dpiIn("writeBusPortEnqReady", Input(Bool()))
val writeBusPortEnqValid = dpiIn("writeBusPortEnqValid", Input(Bool()))
val writeBusPortDeqReady = dpiIn("writeBusPortDeqReady", Input(Bool()))
val writeBusPortDeqValid = dpiIn("writeBusPortDeqValid", Input(Bool()))
}

class LaneRequestMonitor extends LaneMonitor {
val laneRequestValid = dpiIn("laneRequestValid", Input(Bool()))
val laneRequestReady = dpiIn("laneRequestReady", Input(Bool()))
}
class LaneRequestMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneResponseMonitor extends LaneMonitor {
val laneResponseValid = dpiIn("laneResponseValid", Input(Bool()))
class LaneResponseMonitor extends IndexedPerfMonitor with ValidMonitor {
val laneResponseFeedbackValid = dpiIn("laneResponseFeedbackValid", Input(Bool()))
}

class LaneVrfReadMonitor extends LaneMonitor {
val vrfReadAddressChannelValid = dpiIn("vrfReadAddressChannelValid", Input(Bool()))
val vrfReadAddressChannelReady = dpiIn("vrfReadAddressChannelReady", Input(Bool()))
}
class LaneVrfReadMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneVrfWriteMonitor extends LaneMonitor {
val vrfWriteChannelValid = dpiIn("vrfWriteChannelValid", Input(Bool()))
val vrfWriteChannelReady = dpiIn("vrfWriteChannelReady", Input(Bool()))
}
class LaneVrfWriteMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneStatusMonitor extends LaneMonitor {
class LaneStatusMonitor extends IndexedPerfMonitor {
val v0UpdateValid = dpiIn("v0UpdateValid", Input(Bool()))
val writeReadyForLsu = dpiIn("writeReadyForLsu", Input(Bool()))
val vrfReadyToStore = dpiIn("vrfReadyToStore", Input(Bool()))
}

class LaneWriteQueueMonitor extends LaneMonitor {
val writeQueueValid = dpiIn("writeQueueValid", Input(Bool()))
}
class LaneWriteQueueMonitor extends IndexedPerfMonitor with ValidMonitor

class LaneReadBusDequeueMonitor extends LaneMonitor {
val readBusDequeueValid = dpiIn("readBusDequeueValid", Input(Bool()))
}
class LaneReadBusDequeueMonitor extends IndexedPerfMonitor with ValidMonitor

class CrossLaneMonitor extends LaneMonitor {
class CrossLaneMonitor extends IndexedPerfMonitor {
val crossLaneReadValid = dpiIn("crossLaneReadValid", Input(Bool()))
val crossLaneWriteValid = dpiIn("crossLaneWriteValid", Input(Bool()))
}

class LaneReadBusDataMonitor extends LaneMonitor {
val readBusDataReqValid = dpiIn("readBusDataReqValid", Input(Bool()))
}
class LaneReadBusDataMonitor extends IndexedPerfMonitor with ValidMonitor

class LaneWriteBusDataMonitor extends LaneMonitor {
val writeBusDataReqValid = dpiIn("writeBusDataReqValid", Input(Bool()))
}
class LaneWriteBusDataMonitor extends IndexedPerfMonitor with ValidMonitor
// End of Lane monitor

class VRequestMonitor extends PerfMonitor {
val valid = dpiIn("VRequestValid", Input(Bool()))
val ready = dpiIn("VRequestReady", Input(Bool()))
}
class VRequestMonitor extends PerfMonitor with ValidMonitor with ReadyMonitor

class VResponseMonitor extends PerfMonitor {
val valid = dpiIn("VResponseValid", Input(Bool()))
}
class VResponseMonitor extends PerfMonitor with ValidMonitor

class VRequestRegMonitor extends PerfMonitor {
val valid = dpiIn("VRequestRegValid", Input(Bool()))
}
class VRequestRegMonitor extends PerfMonitor with ValidMonitor

class VRequestRegDequeueMonitor extends PerfMonitor {
val valid = dpiIn("VRequestRegDequeueValid", Input(Bool()))
val ready = dpiIn("VRequestRegDequeueReady", Input(Bool()))
}
class VRequestRegDequeueMonitor extends PerfMonitor with ValidMonitor with ReadyMonitor

class VMaskUnitWriteValidMonitor extends PerfMonitor {
val valid = dpiIn("VMaskedUnitWriteValid", Input(Bool()))
}
class VMaskUnitWriteValidMonitor extends PerfMonitor with ValidMonitor

class VMaskUnitWriteValidIndexedMonitor extends PerfMonitor {
val index = dpiIn("index", Input(UInt(32.W)))
val valid = dpiIn("valid", Input(Bool()))
}
class VMaskUnitWriteValidIndexedMonitor extends IndexedPerfMonitor with ValidMonitor

class VMaskUnitReadValidMonitor extends PerfMonitor {
val valid = dpiIn("valid", Input(Bool()))
}
class VMaskUnitReadValidMonitor extends PerfMonitor with ValidMonitor

class VMaskUnitReadValidIndexedMonitor extends PerfMonitor {
val index = dpiIn("index", Input(UInt(32.W)))
val valid = dpiIn("valid", Input(Bool()))
}
class VMaskUnitReadValidIndexedMonitor extends IndexedPerfMonitor with ValidMonitor

class VWarReadResultValidMonitor extends PerfMonitor {
val valid = dpiIn("valid", Input(Bool()))
}
class VWarReadResultValidMonitor extends PerfMonitor with ValidMonitor

class VDataMonitor extends IndexedValidMonitor
class VDataMonitor extends IndexedPerfMonitor with ValidMonitor

class VSelectffoIndexMonitor extends ValidMonitor

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