[t1rocket] fix wrong rd when meet rvc instruction's 3-bit rd

chipsalliance · Aug 19, 2024 · 5f3417d · 5f3417d
1 parent 9a26a56
commit 5f3417d
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Showing 2 changed files with 33 additions and 27 deletions.
diff --git a/t1rocketemu/offline/src/json_events.rs b/t1rocketemu/offline/src/json_events.rs
@@ -184,8 +184,8 @@ impl JsonEventRunner for SpikeRunner {
       se.describe_insn()
     );
 
-    assert_eq!(idx as u32, se.rd_idx, "idx should be equal to se.rd_idx");
-    assert_eq!(data, se.rd_bits, "data should be equal to se.rd_bits");
+    assert!(idx as u32 == se.rd_idx, "rtl idx({:#x}) should be equal to spike idx({:#x})", idx, se.rd_idx);
+    assert!(data == se.rd_bits, "rtl data({:#x}) should be equal to spike data({:#x})", data, se.rd_bits);
 
     Ok(())
   }

diff --git a/t1rocketemu/spike_rs/src/spike_event.rs b/t1rocketemu/spike_rs/src/spike_event.rs
@@ -401,32 +401,38 @@ impl SpikeEvent {
     // xx0100 <- csr
     let reg_write_size = state.get_reg_write_size();
     // TODO: refactor it.
-    (0..reg_write_size).for_each(|idx| match state.get_reg_write_index(idx) & 0xf {
-      0b0000 => {
-        // scalar rf
-        let data = state.get_reg(self.rd_idx, false);
-        self.is_rd_written = true;
-        self.rd_bits = data;
-        trace!(
-          "ScalarRFChange: idx={:02x}, data={:08x}",
-          self.rd_idx,
-          self.rd_bits
-        );
-      }
-      0b0001 => {
-        let data = state.get_reg(self.rd_idx, true);
-        self.is_rd_written = true;
-        self.rd_bits = data;
-        trace!(
-          "FloatRFChange: idx={:02x}, data={:08x}",
-          self.rd_idx,
-          self.rd_bits
-        );
+    (0..reg_write_size).for_each(|idx| {
+      let rd_idx_type = state.get_reg_write_index(idx);
+      self.rd_idx = rd_idx_type >> 4;
+      match rd_idx_type & 0xf {
+        0b0000 => {
+          // scalar rf
+          if self.rd_idx != 0 {
+            let data = state.get_reg(self.rd_idx, false);
+            self.is_rd_written = true;
+            self.rd_bits = data;
+            trace!(
+              "ScalarRFChange: idx={:02x}, data={:08x}",
+              self.rd_idx,
+              self.rd_bits
+            );
+          }
+        }
+        0b0001 => {
+          let data = state.get_reg(self.rd_idx, true);
+          self.is_rd_written = true;
+          self.rd_bits = data;
+          trace!(
+            "FloatRFChange: idx={:02x}, data={:08x}",
+            self.rd_idx,
+            self.rd_bits
+          );
+        }
+        _ => trace!(
+          "UnknownRegChange, idx={:02x}, spike detect unknown reg change",
+          self.rd_idx
+        ),
       }
-      _ => trace!(
-        "UnknownRegChange, idx={:02x}, spike detect unknown reg change",
-        state.get_reg_write_index(idx)
-      ),
     });
 
     Ok(())