add attribute for vwsll

chipsalliance · Jul 23, 2024 · 5d3c08b · 5d3c08b
1 parent 09cd0c5
commit 5d3c08b
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Showing 7 changed files with 32 additions and 12 deletions.
diff --git a/t1/src/decoder/attribute/isCrossread.scala b/t1/src/decoder/attribute/isCrossread.scala
@@ -56,6 +56,10 @@ object isCrossread {
       "vwsub.wx",
       "vwsubu.wv",
       "vwsubu.wx",
+      // rv_zvbb
+      "vwsll.vv",
+      "vwsll.vx",
+      "vwsll.vi",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/isCrosswrite.scala b/t1/src/decoder/attribute/isCrosswrite.scala
@@ -46,6 +46,10 @@ object isCrosswrite {
       "vwsubu.vx",
       "vwsubu.wv",
       "vwsubu.wx",
+      // rv_zvbb
+      "vwsll.vv",
+      "vwsll.vx",
+      "vwsll.vi",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/isScheduler.scala b/t1/src/decoder/attribute/isScheduler.scala
@@ -274,5 +274,5 @@ object isScheduler {
 }
 
 case class isScheduler(value: TriState) extends BooleanDecodeAttribute {
-  override val description: String = "lane will send request to Sequencer and wait ack from Sequencer. instructions that will communicate with T1 top module.*/ "
+  override val description: String = "lane will send request to Sequencer and wait ack from Sequencer. Instructions that will communicate with T1 top module.*/ "
 }
diff --git a/t1/src/decoder/attribute/isSwrite.scala b/t1/src/decoder/attribute/isSwrite.scala
@@ -224,5 +224,5 @@ object isSwrite {
 }
 
 case class isSwrite(value: TriState) extends BooleanDecodeAttribute {
-  override val description: String = "sWrite -> targetRd || readOnly || crossWrite || maskDestination || reduce || loadStore instruction will write vd or rd(scalar) from outside of lane. It will request vrf wait, and lane will not write. "
+  override val description: String = "sWrite -> targetRd || readOnly || crossWrite || maskDestination || reduce || loadStore instruction will write vd or rd(scalar) from outside of lane. It will request vrf wait, and lane will not write. No write to vd when isSwrite is True!!!"
 }
diff --git a/t1/src/decoder/attribute/isVtype.scala b/t1/src/decoder/attribute/isVtype.scala
@@ -186,6 +186,7 @@ object isVtype {
       "vrol.vv",
       "vror.vv",
       "vwsll.vv",
+      "vwsll.vv",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/isZvbb.scala b/t1/src/decoder/attribute/isZvbb.scala
@@ -27,6 +27,9 @@ object isZvbb {
       "vror.vv",
       "vror.vx",
       "vror.vi",
+      "vwsll.vv",
+      "vwsll.vx",
+      "vwsll.vi",
     ) else Seq()
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/zvbbUop.scala b/t1/src/decoder/attribute/zvbbUop.scala
@@ -30,46 +30,54 @@ object ZvbbUOP {
   }
   def t0(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
-        "vbrev.v"
+      "vbrev.v"
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
   def t1(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
-        "vbrev8.v"
+      "vbrev8.v"
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
   def t2(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
-        "vrev8.v"
+      "vrev8.v"
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
   def t3(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
-        "vclz.v"
+      "vclz.v"
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
   def t4(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
-        "vctz.v"
+      "vctz.v"
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
   def t5(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
-        "vrol.vv",
-        "vrol.vx",
+      "vrol.vv",
+      "vrol.vx",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
   def t6(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
-        "vror.vv",
-        "vror.vx",
-        "vror.vi",
+      "vror.vv",
+      "vror.vx",
+      "vror.vi",
+    )
+    allMatched.contains(t1DecodePattern.instruction.name)
+  }
+  def t7(t1DecodePattern: T1DecodePattern): Boolean = {
+    val allMatched: Seq[String] = Seq(
+      "vwsll.vv",
+      "vwsll.vx",
+      "vwsll.vi",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }