[rtl] fix read only chaining.

chipsalliance · Nov 16, 2024 · 59443ac · 59443ac
1 parent 097e178
commit 59443ac
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/vrf/WriteCheck.scala b/t1/src/vrf/WriteCheck.scala
@@ -54,7 +54,7 @@ class WriteCheck(val parameter: VRFParam) extends Module {
   )
   val notHitVs1:    Bool = (checkOH & vs1Mask) === 0.U
   val war1:         Bool = record.bits.vs1.valid && check.vd(4, 3) === record.bits.vs1.bits(4, 3) && notHitVs1
-  val maskForVs2:   UInt = record.bits.elementMask | Fill(parameter.elementSize, record.bits.onlyRead)
+  val maskForVs2:   UInt = record.bits.elementMask & Fill(parameter.elementSize, !record.bits.onlyRead)
   val vs2Mask:      UInt = (((-1.S(parameter.elementSize.W)).asUInt ## maskForVs2) <<
     ((8.U + record.bits.vs2(2, 0) - record.bits.vd.bits(2, 0)) << parameter.vrfOffsetBits).asUInt).asUInt(
     2 * 8 * parameter.singleGroupSize - 1,