[rtl] Slots can always be shifted when slot idle.

chipsalliance · May 22, 2024 · 58abb69 · 58abb69
1 parent 5a08140
commit 58abb69
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Showing 2 changed files with 9 additions and 8 deletions.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -462,6 +462,9 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   /** request from slot to vfu. */
   val requestVec: Vec[SlotRequestToVFU] = Wire(Vec(parameter.chainingSize, new SlotRequestToVFU(parameter)))
 
+  val requestDecode: Seq[DecodeBundle] =
+    Seq.tabulate(parameter.chainingSize) { _ => WireDefault(slotControl.head.laneRequest.decodeResult)}
+
   /** response from vfu to slot. */
   val responseVec: Vec[ValidIO[VFUResponseToSlot]] = Wire(Vec(parameter.chainingSize, Valid(new VFUResponseToSlot(parameter))))
 
@@ -549,7 +552,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
       if(isLastSlot) {
         slotCanShift(index) := pipeClear && pipeFinishVec(index)
       } else {
-        slotCanShift(index) := pipeClear
+        slotCanShift(index) := true.B
       }
 
       val laneState: LaneState = Wire(new LaneState(parameter))
@@ -559,6 +562,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
       val executionUnit: Instance[LaneExecutionBridge] = Instantiate(new LaneExecutionBridge(parameter, isLastSlot, index))
       val stage3: Instance[LaneStage3] = Instantiate(new LaneStage3(parameter, isLastSlot))
 
+      requestDecode(index) := executionUnit.requestDecode
       // slot state
       laneState.vSew1H := vSew1H
       laneState.loadStore := record.laneRequest.loadStore
@@ -836,17 +840,11 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     assert(queue.io.enq.ready || !port.enq.valid)
     port.enqRelease := queue.io.deq.fire
   }
-  // convert data types
-
-
-  // VFU
-  // TODO: reuse logic, adder, multiplier datapath
-  val decodeResultVec: Seq[DecodeBundle] = slotControl.map(_.laneRequest.decodeResult)
 
   val vfus: Seq[Instance[VFUModule]] = instantiateVFU(parameter.vfuInstantiateParameter)(
     requestVec,
     executeEnqueueValid,
-    decodeResultVec,
+    requestDecode,
     executeEnqueueFire,
     responseVec,
     executeOccupied,

diff --git a/t1/src/laneStage/LaneExecutionBridge.scala b/t1/src/laneStage/LaneExecutionBridge.scala
@@ -58,6 +58,8 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
   // request to vfu
   @public
   val vfuRequest: DecoupledIO[SlotRequestToVFU] = IO(Decoupled(new SlotRequestToVFU(parameter)))
+  @public
+  val requestDecode: DecodeBundle = IO(Output(Decoder.bundle(parameter.fpuEnable)))
   // response from vfu
   @public
   val dataResponse: ValidIO[VFUResponseToSlot] = IO(Flipped(Valid(new VFUResponseToSlot(parameter))))
@@ -271,6 +273,7 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
     executionRecord.csr.vSew + 1.U,
     executionRecord.csr.vSew
   )
+  requestDecode := executionRecord.decodeResult
   val shifterSizeBit = Mux(executionRecord.crossReadVS2, executionRecord.vSew1H(1, 0), executionRecord.vSew1H(2, 1))
   vfuRequest.bits.shifterSize := VecInit(cutUInt(finalSource1, 8).map(data =>
     Mux1H(