[rtl] float order reduce sum.

chipsalliance · Nov 14, 2024 · 57a89b3 · 57a89b3
1 parent 05e5e05
commit 57a89b3
Showing 1 changed file with 2 additions and 4 deletions.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -294,15 +294,13 @@ class MaskUnit(parameter: T1Parameter) extends Module {
     val rowWidth      = parameter.datapathWidth * parameter.laneNumber / 8
     val rowWidthLog:        Int  = log2Ceil(rowWidth)
     val lastGroupRemaining: UInt = changeUIntSize(lastByteIndex, rowWidthLog)
-    val lastGroupMisAlign:  Bool = lastGroupRemaining.orR
     // get last group index
     val lastRowIndex = (lastByteIndex >> rowWidthLog).asUInt
 
     // for last group remainder lastGroupRemaining
     val laneDatalog       = log2Ceil(parameter.datapathWidth)
-    val lastLaneIndex     = (lastGroupRemaining >> laneDatalog).asUInt +
-      changeUIntSize(lastGroupRemaining, laneDatalog).orR
-    val lastGroupDataNeed = (~scanLeftOr(UIntToOH(lastLaneIndex))).asUInt
+    val lastLaneIndex     = (lastGroupRemaining >> laneDatalog).asUInt
+    val lastGroupDataNeed = scanRightOr(UIntToOH(lastLaneIndex))
     (lastRowIndex, lastGroupDataNeed)
   }