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[configs] add v4096-l8-b4-fp and v4096-l32-b4-fp
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Signed-off-by: Avimitin <[email protected]>
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Avimitin authored and sequencer committed Jan 18, 2024
1 parent 1354de1 commit 5465539
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Showing 2 changed files with 376 additions and 0 deletions.
188 changes: 188 additions & 0 deletions configs/v4096-l32-b4-fp.json
Original file line number Diff line number Diff line change
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{
"parameter": {
"xLen": 32,
"vLen": 4096,
"datapathWidth": 32,
"laneNumber": 32,
"physicalAddressWidth": 32,
"chainingSize": 4,
"vrfWriteQueueSize": 4,
"fpuEnable": true,
"instructionQueueSize": 8,
"memoryBankSize": 4,
"lsuVRFWriteQueueSize": 96,
"portFactor": 1,
"vfuInstantiateParameter": {
"slotCount": 4,
"logicModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.MaskedLogic"
},
[
0,
1,
2,
3
]
]
],
"aluModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneAdder"
},
[
0
]
],
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneAdder"
},
[
1
]
],
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneAdder"
},
[
2
]
],
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneAdder"
},
[
3
]
]
],
"shifterModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneShifter"
},
[
0,
1,
2,
3
]
]
],
"mulModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneMul"
},
[
0,
1,
2,
3
]
]
],
"divModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneDiv"
},
[
0,
1,
2,
3
]
]
],
"otherModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"vlMaxBits": 11,
"groupNumberBits": 6,
"laneNumberBits": 3,
"dataPathByteWidth": 4,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.OtherUnit"
},
[
0,
1,
2,
3
]
]
],
"floatModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 3
},
"generator": "org.chipsalliance.t1.rtl.LaneFloat"
},
[
0,
1,
2,
3
]
]
],
"divfpModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneDivFP"
},
[0, 1, 2, 3]
]
]
}
},
"generator": "org.chipsalliance.t1.rtl.V"
}
188 changes: 188 additions & 0 deletions configs/v4096-l8-b4-fp.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,188 @@
{
"parameter": {
"xLen": 32,
"vLen": 4096,
"datapathWidth": 32,
"laneNumber": 8,
"physicalAddressWidth": 32,
"chainingSize": 4,
"vrfWriteQueueSize": 4,
"fpuEnable": true,
"instructionQueueSize": 8,
"memoryBankSize": 4,
"lsuVRFWriteQueueSize": 96,
"portFactor": 1,
"vfuInstantiateParameter": {
"slotCount": 4,
"logicModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.MaskedLogic"
},
[
0,
1,
2,
3
]
]
],
"aluModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneAdder"
},
[
0
]
],
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneAdder"
},
[
1
]
],
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneAdder"
},
[
2
]
],
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneAdder"
},
[
3
]
]
],
"shifterModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneShifter"
},
[
0,
1,
2,
3
]
]
],
"mulModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneMul"
},
[
0,
1,
2,
3
]
]
],
"divModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneDiv"
},
[
0,
1,
2,
3
]
]
],
"otherModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"vlMaxBits": 11,
"groupNumberBits": 6,
"laneNumberBits": 3,
"dataPathByteWidth": 4,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.OtherUnit"
},
[
0,
1,
2,
3
]
]
],
"floatModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 3
},
"generator": "org.chipsalliance.t1.rtl.LaneFloat"
},
[
0,
1,
2,
3
]
]
],
"divfpModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 0
},
"generator": "org.chipsalliance.t1.rtl.LaneDivFP"
},
[0, 1, 2, 3]
]
]
}
},
"generator": "org.chipsalliance.t1.rtl.V"
}

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