fix connection in RocketTileInterface

chipsalliance · Aug 9, 2024 · 3f5cfc7 · 3f5cfc7
1 parent 25572c3
commit 3f5cfc7
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Showing 2 changed files with 6 additions and 5 deletions.
diff --git a/rocketemu/src/TestBench.scala b/rocketemu/src/TestBench.scala
@@ -67,6 +67,7 @@ class TestBench(generator: SerializableModuleGenerator[RocketTile, RocketTilePar
   dut.io.mtip := 0.U
   dut.io.meip := 0.U
   dut.io.msip := 0.U
+  dut.io.seip.foreach(_ := 0.U)
   dut.io.buserror := 0.U
 
   // get resetVector from simulator

diff --git a/rocketv/src/RocketTile.scala b/rocketv/src/RocketTile.scala
@@ -375,11 +375,11 @@ class RocketTileInterface(parameter: RocketTileParameter) extends Bundle {
   val mtip:  Bool = Input(Bool())
   val msip:  Bool = Input(Bool())
   val meip:  Bool = Input(Bool())
-  val seip:  Option[Bool] = Option.when(parameter.usingSupervisor)(Bool())
-  val lip:   Vec[Bool] = Vec(parameter.nLocalInterrupts, Bool())
-  val nmi = Option.when(parameter.usingNMI)(Bool())
-  val nmiInterruptVector = Option.when(parameter.usingNMI)(UInt(parameter.resetVectorBits.W))
-  val nmiIxceptionVector = Option.when(parameter.usingNMI)(UInt(parameter.resetVectorBits.W))
+  val seip:  Option[Bool] = Option.when(parameter.usingSupervisor)(Input(Bool()))
+  val lip:   Vec[Bool] = Input(Vec(parameter.nLocalInterrupts, Bool()))
+  val nmi = Option.when(parameter.usingNMI)(Input(Bool()))
+  val nmiInterruptVector = Option.when(parameter.usingNMI)(Input(UInt(parameter.resetVectorBits.W)))
+  val nmiIxceptionVector = Option.when(parameter.usingNMI)(Input(UInt(parameter.resetVectorBits.W)))
   // TODO: buserror should be handled by NMI
   val buserror: Bool = Input(Bool())
   val wfi:      Bool = Output(Bool())