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@sequencer
sequencer committed Jul 25, 2024
1 parent a94002f commit 3f4c88b
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Showing 3 changed files with 93 additions and 26 deletions.
44 changes: 28 additions & 16 deletions rocketv/src/Bundle.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
package org.chipsalliance.rocketv

import chisel3._
import chisel3.util.{Cat, Decoupled, DecoupledIO, Valid, isPow2, log2Ceil}
import chisel3.util.{Cat, Decoupled, DecoupledIO, Valid, ValidIO, isPow2, log2Ceil}

// This file defines Bundle shared in the project.
// all Bundle only have datatype without any helper or functions, while they only exist in the companion Bundle.
Expand Down Expand Up @@ -1400,30 +1400,42 @@ class FrontendBundle(vaddrBitsExtended: Int, vaddrBits: Int, asidBits: Int, entr
}

// Interface between T1 <> Rocket integration
class RocketCoreToT1 extends Bundle {
val issue: Valid[T1Issue] = Valid(new T1Issue)
val retire: T1Retire = Flipped(new T1Retire)
class RocketCoreToT1(xLen: Int, vlWidth: Int) extends Bundle {
val issue: DecoupledIO[T1Issue] = Decoupled(new T1Issue(xLen, vlWidth))
val retire: T1Retire = Flipped(new T1Retire(xLen))
}

class T1Issue extends Bundle {
class T1Issue(xLen: Int, vlWidth: Int) extends Bundle {
val instruction: UInt = UInt(32.W)
val rs1Data: UInt = UInt(32.W)
val rs2Data: UInt = UInt(32.W)
val rs1Data: UInt = UInt(xLen.W)
val rs2Data: UInt = UInt(xLen.W)
val vtype: UInt = UInt(32.W)
val vl: UInt = UInt(32.W)
val vstart: UInt = UInt(32.W)
val vcsr: UInt = UInt(32.W)
}

class T1RdRetire extends Bundle {
val rd: UInt = UInt(5.W)
val data: UInt = UInt(32.W)
val fp: Bool = Bool()
object T1Issue {
def vlmul(issue: T1Issue): UInt = issue.vtype(2, 0)
def vsew(issue: T1Issue): UInt = issue.vtype(5, 3)
def vta(issue: T1Issue): Bool = issue.vtype(6)
def vma(issue: T1Issue): Bool = issue.vtype(7)
def vxrm(issue: T1Issue): UInt = issue.vcsr(2, 1)
}

class T1RdRetire(xLen: Int) extends Bundle {
val rdAddress: UInt = UInt(5.W)
val rdData: UInt = UInt(xLen.W)
val isFp: Bool = Bool()
}

class T1CSRRetire extends Bundle {
val vxsat: UInt = UInt(32.W)
val vxsat: UInt = UInt(32.W)
val fflag: UInt = UInt(32.W)
}

class T1Retire extends Bundle {
val rd = Valid(new T1RdRetire)
val csr = Valid(new T1CSRRetire)
val mem = Valid(new Bundle {})
class T1Retire(xLen: Int) extends Bundle {
val rd: Valid[T1RdRetire] = Valid(new T1RdRetire(xLen))
val csr: Valid[T1CSRRetire] = Valid(new T1CSRRetire)
val mem: Valid[Bundle] = Valid(new Bundle {})
}
17 changes: 9 additions & 8 deletions rocketv/src/RocketCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,7 @@ class RocketInterface(parameter: RocketParameter) extends Bundle {
)
)
val fpu = parameter.fLen.map(fLen => Flipped(new FPUCoreIO(parameter.hartIdLen, parameter.xLen, fLen)))
val t1 = Option.when(parameter.usingT1)(new RocketCoreToT1)
val t1 = Option.when(parameter.usingT1)(new RocketCoreToT1(parameter.xLen, parameter.vLen))
val bpwatch = Output(Vec(parameter.nBreakpoints, new BPWatch))
val cease = Output(Bool())
val wfi = Output(Bool())
Expand Down Expand Up @@ -1342,9 +1342,9 @@ class Rocket(val parameter: RocketParameter)
fpu.keep_clock_enabled := false.B
}

// TODO: T1 only logic
io.t1.foreach { t1 =>
// Send instruction to T1 when write back.
// TODO: make it configurable
// T1 Issue
val maxCount: Int = 32
val t1IssueQueue = Module(new Queue(chiselTypeOf(t1.issue.bits), maxCount))
t1IssueQueue.io.enq.valid := wbRegValid && !replayWbCommon && wbRegDecodeOutput(parameter.decoderParameter.vector)
Expand All @@ -1353,6 +1353,7 @@ class Rocket(val parameter: RocketParameter)
t1IssueQueue.io.enq.bits.rs2Data := wbRegRS2
t1.issue.valid := t1IssueQueue.io.deq.valid
t1.issue.bits := t1IssueQueue.io.deq.bits
// For each different retirements, it should maintain different scoreboard
val t1MemoryRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.mem.bits), maxCount))
val t1CSRRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.csr.bits), maxCount))
val t1XRDRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.rd.bits), maxCount))
Expand Down Expand Up @@ -1386,22 +1387,22 @@ class Rocket(val parameter: RocketParameter)
vectorLSUEmpty.foreach(_ := lsuEmpty)
vectorQueueFull.foreach(_ := vectorFull)

val vectorTryToWriteRd = t1.retire.rd.valid && !t1.retire.rd.bits.fp
val vectorTryToWriteFP = t1.retire.rd.valid && t1.retire.rd.bits.fp
val vectorTryToWriteRd = t1.retire.rd.valid && !t1.retire.rd.bits.isFp
val vectorTryToWriteFP = t1.retire.rd.valid && t1.retire.rd.bits.isFp
// TODO: maintain queue here?
t1XRDRetireQueue.io.deq.ready := (!(wbWxd || (dmemResponseReplay && dmemResponseXpu)) || !vectorTryToWriteRd) && (!(dmemResponseReplay && dmemResponseFpu) || !vectorTryToWriteFP)
t1CSRRetireQueue.io.deq.ready := (!(wbWxd || (dmemResponseReplay && dmemResponseXpu)) || !vectorTryToWriteRd) && (!(dmemResponseReplay && dmemResponseFpu) || !vectorTryToWriteFP)
t1MemoryRetireQueue.io.deq.ready := (!(wbWxd || (dmemResponseReplay && dmemResponseXpu)) || !vectorTryToWriteRd) && (!(dmemResponseReplay && dmemResponseFpu) || !vectorTryToWriteFP)

when(t1.retire.rd.fire && vectorTryToWriteRd) {
longlatencyWdata := t1.retire.rd.bits.data
longlatencyWaddress := t1.retire.rd.bits.rd
longlatencyWdata := t1.retire.rd.bits.rdData
longlatencyWaddress := t1.retire.rd.bits.rdAddress
longLatencyWenable := true.B
}
io.fpu.foreach { fpu =>
when(!(dmemResponseValid && dmemResponseFpu)) {
fpu.dmem_resp_val := t1.retire.mem.fire && vectorTryToWriteFP
fpu.dmem_resp_data := t1.retire.rd.bits.data
fpu.dmem_resp_data := t1.retire.rd.bits.rdData
// todo: 32 bit only
fpu.dmem_resp_type := 2.U
// todo: connect tag
Expand Down
58 changes: 56 additions & 2 deletions t1rocketv/src/T1RocketTile.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -27,26 +27,46 @@ case class T1RocketTileParameter(
useAsyncReset: Boolean,
clockGate: Boolean,
instructionSets: Set[String],
// Fixed to M, in the future, we will add S, but no U
priv: String,
// Current hardId is only 0
hartIdLen: Int,
// always false
useBPWatch: Boolean,
// use default
mcontextWidth: Int,
// use default
scontextWidth: Int,
// 0
asidBits: Int,
// use paddr
resetVectorBits: Int,
// use 0
nBreakpoints: Int,
// disable TLB?
dtlbNWays: Int,
// disable TLB?
dtlbNSets: Int,
// disable TLB?
itlbNSets: Int,
// disable TLB?
itlbNWays: Int,
// disable TLB?
itlbNSectors: Int,
// disable TLB?
itlbNSuperpageEntries: Int,
// disable TLB?
nPTECacheEntries: Int,
// disable TLB?
nL2TLBWays: Int,
// disable TLB?
nL2TLBEntries: Int,
// disable 32 bits? 4G?
paddrBits: Int,
// should be configurable
cacheBlockBytes: Int,
nPMPs: Int,
// T1 doens't check exception.
legal: BitSet,
cacheable: BitSet,
read: BitSet,
Expand All @@ -56,28 +76,48 @@ case class T1RocketTileParameter(
arithmetic: BitSet,
exec: BitSet,
sideEffects: BitSet,
// use default
btbEntries: Int,
// use default
btbNMatchBits: Int,
// use default
btbUpdatesOutOfOrder: Boolean,
// use default
nPages: Int,
// use default
nRAS: Int,
// use default
bhtParameter: Option[BHTParameter],
mulDivLatency: Int,
// use default
mulDivLatency: Int,
// use default
divUnroll: Int,
// use default
divEarlyOut: Boolean,
// use default
divEarlyOutGranularity: Int,
// use default
mulUnroll: Int,
// use default
mulEarlyOut: Boolean,
// use default
sfmaLatency: Int,
// use default
dfmaLatency: Int,
// use default
divSqrt: Boolean,
// always true: use FENCE.I
flushOnFenceI: Boolean,
// use default
fastLoadByte: Boolean,
// use default
fastLoadWord: Boolean,
dcacheNSets: Int,
dcacheNWays: Int,
dcacheRowBits: Int,
// use default
maxUncachedInFlight: Int,
// use default
separateUncachedResp: Boolean,
iCacheNSets: Int,
iCacheNWays: Int,
Expand Down Expand Up @@ -187,7 +227,8 @@ case class T1RocketTileParameter(
fastLoadByte,
fastLoadWord,
dcacheNSets,
flushOnFenceI
flushOnFenceI,
true
)

def hellaCacheParameter: HellaCacheParameter = HellaCacheParameter(
Expand Down Expand Up @@ -307,6 +348,9 @@ case class T1RocketTileParameter(
def loadStoreParameter: AXI4BundleParameter = hellaCacheParameter.loadStoreParameter

def dtimParameter: Option[AXI4BundleParameter] = hellaCacheParameter.dtimParameter

def t1HighBandwidthParameter: AXI4BundleParameter = ???
def t1HightOutstandingParameter: AXI4BundleParameter = ???
}

class T1RocketTileInterface(parameter: T1RocketTileParameter) extends Bundle {
Expand Down Expand Up @@ -339,6 +383,9 @@ class T1RocketTileInterface(parameter: T1RocketTileParameter) extends Bundle {
org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(parameter.loadStoreParameter)
val dtimAXI: Option[AXI4RWIrrevocable] =
parameter.dtimParameter.map(p => Flipped(org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(p)))

val highBandwidthAXI: AXI4RWIrrevocable = org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(parameter.t1HighBandwidthParameter)
val highOutstandingAXI: AXI4RWIrrevocable = org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(parameter.t1HightOutstandingParameter)
}

class RocketTile(val parameter: T1RocketTileParameter)
Expand Down Expand Up @@ -385,6 +432,9 @@ class RocketTile(val parameter: T1RocketTileParameter)
hellaCacheArbiter.io.requestor(0) <> rocket.io.dmem
rocket.io.ptw <> ptw.io.dpath
rocket.io.fpu.zip(fpu.map(_.io.core)).foreach { case (core, fpu) => core <> fpu }
// match connect
t1.io.issue <> rocket.io.t1.get.issue
rocket.io.t1.get.retire <> t1.io.retire
// used by trace module
rocket.io.bpwatch := DontCare
// don't use for now, this is design for report the custom cease status.
Expand Down Expand Up @@ -420,4 +470,8 @@ class RocketTile(val parameter: T1RocketTileParameter)
fpu.io.cp_req <> DontCare
fpu.io.cp_resp <> DontCare
}
t1.io.clock := io.clock
t1.io.reset := io.reset
io.highBandwidthAXI <> t1.io.highBandwidthLoadStorePort
io.highOutstandingAXI <> t1.io.indexedLoadStorePort
}

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