[rtl] fix widen reduce.

chipsalliance · Nov 13, 2024 · 32d2b80 · 32d2b80
1 parent e4e5295
commit 32d2b80
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Showing 2 changed files with 13 additions and 11 deletions.
diff --git a/t1/src/mask/MaskReduce.scala b/t1/src/mask/MaskReduce.scala
@@ -38,7 +38,7 @@ class MaskReduce(parameter: T1Parameter) extends Module {
 
   // todo: uop decode
   val order:    Bool = in.bits.uop === "b101".U
-  val reqWiden: Bool = in.bits.uop === "b001".U
+  val reqWiden: Bool = in.bits.uop === "b001".U || in.bits.uop(2, 1) === "b11".U
 
   val eew1H:         UInt = UIntToOH(in.bits.eew)(2, 0)
   val nextFoldCount: Bool = eew1H(0) && !reqWiden
@@ -72,7 +72,8 @@ class MaskReduce(parameter: T1Parameter) extends Module {
   val floatType:  Bool = reqReg.uop(2) || reqReg.uop(1, 0).andR
   val NotAdd:     Bool = reqReg.uop(1)
   val widen:      Bool = reqReg.uop === "b001".U || reqReg.uop(2, 1) === "b11".U
-  val needFold:   Bool = eew1HReg(0) || (eew1HReg(1) && !widen)
+  //eew1HReg(0) || (eew1HReg(1) && !widen)
+  val needFold:   Bool = false.B
   val writeEEW:   UInt = reqReg.eew + widen
   val writeEEW1H: UInt = UIntToOH(writeEEW)(2, 0)
   val writeMask:  UInt = Fill(2, writeEEW1H(2)) ## !writeEEW1H(0) ## true.B
@@ -120,12 +121,13 @@ class MaskReduce(parameter: T1Parameter) extends Module {
     }
   }
 
-  val enqWriteMask:   UInt = Fill(2, in.bits.eew(1)) ## in.bits.eew.orR ## true.B
+  val widenEnqMask:   UInt = Fill(2, in.bits.eew.orR) ## true.B ## true.B
+  val normalMask:   UInt = Fill(2, in.bits.eew(1)) ## in.bits.eew.orR ## true.B
+  val enqWriteMask: UInt = Mux(reqWiden, widenEnqMask, normalMask)
   val updateInitMask: UInt = FillInterleaved(8, enqWriteMask)
   val updateMask:     UInt = FillInterleaved(8, writeMask)
   when(newInstruction) {
-    // todo: update reduceInit when first in.fire
-    reduceInit     := in.bits.readVS1 & updateInitMask
+    reduceInit     := Mux(pop, 0.U, in.bits.readVS1 & updateInitMask)
     crossFoldCount := 0.U
     lastFoldCount  := nextFoldCount
   }
@@ -171,7 +173,7 @@ class MaskReduce(parameter: T1Parameter) extends Module {
   adder.request.src    := VecInit(Seq(reduceInit, source2Select))
   adder.request.opcode := reqReg.aluUop
   adder.request.sign   := reqReg.sign
-  adder.request.vSew   := reqReg.eew
+  adder.request.vSew   := 2.U
 
   floatAdder.foreach { fAdder =>
     fAdder.io.a            := reduceInit
@@ -203,7 +205,7 @@ class MaskReduce(parameter: T1Parameter) extends Module {
     Mux(NotAdd, logicUnit.resp, adder.response.data)
   )
 
-  out.valid     := outValid
+  out.valid     := outValid && !pop
   out.bits.data := Mux(updateResult, reduceResult, reduceInit)
-  out.bits.mask := writeMask & Fill(4, validInst && !pop)
+  out.bits.mask := writeMask & Fill(4, validInst)
 }
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -247,7 +247,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val noSource: Bool = mv || viota
 
   val allGroupExecute: Bool = maskDestinationType || unitType(2) || compress || ffo
-  val useDefaultSew:   Bool = unitType(0)
+  val useDefaultSew:   Bool = unitType(0) && !gather16
   // todo: decode ?
   // Indicates how many times a set of data will be executed
   // 0 -> 4 times
@@ -258,7 +258,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
       useDefaultSew               -> instReg.sew,
       // extend
       (unitType(3) && subType(2)) -> 0.U,
-      (unitType(3) && subType(1)) -> 1.U,
+      (unitType(3) && subType(1) || gather16) -> 1.U,
       allGroupExecute             -> 2.U
     )
   )
@@ -369,7 +369,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val dataSourceSew:   UInt = Mux(
     unitType(3),
     instReg.sew - instReg.decodeResult(Decoder.topUop)(2, 1),
-    instReg.sew
+    Mux(gather16, 1.U, instReg.sew)
   )
   val dataSourceSew1H: UInt = UIntToOH(dataSourceSew)(2, 0)