[test] fix isVector probe.

chipsalliance · Aug 25, 2024 · 27d742e · 27d742e
1 parent e0d86f8
commit 27d742e
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
@@ -1473,7 +1473,8 @@ class Rocket(val parameter: RocketParameter)
         probeWire.waitWaddr := wbWaddr
         // vector commit || vector write rd
         probeWire.isVector := io.t1.map { t1 =>
-          wbRegDecodeOutput(parameter.decoderParameter.vector) && !wbRegDecodeOutput(parameter.decoderParameter.vectorCSR)
+          wbRegValid && wbRegDecodeOutput(parameter.decoderParameter.vector) &&
+            !wbRegDecodeOutput(parameter.decoderParameter.vectorCSR)
         }.getOrElse(false.B) || t1RetireQueue.map(q => q.io.deq.fire).getOrElse(false.B)
         probeWire.idle := vectorEmpty