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[ci] update t1 test case cycle data
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github-actions authored and Avimitin committed Nov 21, 2024
1 parent cd000a2 commit 200f14b
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Showing 8 changed files with 73 additions and 77 deletions.
11 changes: 5 additions & 6 deletions .github/designs/benchmark_dlen1024_vlen1024_fp/t1rocketemu.json
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@@ -1,7 +1,6 @@
{
"rvv_bench.ascii_to_utf32": -1,
"rvv_bench.byteswap": -1,
"rvv_bench.memcpy": -1,
"rvv_bench.memset": -1
}

"rvv_bench.ascii_to_utf32": 229134,
"rvv_bench.byteswap": 390998,
"rvv_bench.memcpy": 671689,
"rvv_bench.memset": 285695
}
11 changes: 5 additions & 6 deletions .github/designs/benchmark_dlen128_vlen1024_fp/t1rocketemu.json
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
{
"rvv_bench.ascii_to_utf32": -1,
"rvv_bench.byteswap": -1,
"rvv_bench.memcpy": -1,
"rvv_bench.memset": -1
}

"rvv_bench.ascii_to_utf32": 232277,
"rvv_bench.byteswap": 415827,
"rvv_bench.memcpy": 674728,
"rvv_bench.memset": 295430
}
11 changes: 5 additions & 6 deletions .github/designs/benchmark_dlen256_vlen1024_fp/t1rocketemu.json
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
{
"rvv_bench.ascii_to_utf32": -1,
"rvv_bench.byteswap": -1,
"rvv_bench.memcpy": -1,
"rvv_bench.memset": -1
}

"rvv_bench.ascii_to_utf32": 230473,
"rvv_bench.byteswap": 401865,
"rvv_bench.memcpy": 673282,
"rvv_bench.memset": 289560
}
11 changes: 5 additions & 6 deletions .github/designs/benchmark_dlen512_vlen1024_fp/t1rocketemu.json
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
{
"rvv_bench.ascii_to_utf32": -1,
"rvv_bench.byteswap": -1,
"rvv_bench.memcpy": -1,
"rvv_bench.memset": -1
}

"rvv_bench.ascii_to_utf32": 229558,
"rvv_bench.byteswap": 394622,
"rvv_bench.memcpy": 672189,
"rvv_bench.memset": 286880
}
6 changes: 3 additions & 3 deletions .github/designs/blastoise/t1emu.json
Original file line number Diff line number Diff line change
Expand Up @@ -13,11 +13,11 @@
"intrinsic.softmax": 7032,
"rvv_bench.ascii_to_utf16": 11282,
"rvv_bench.ascii_to_utf32": 4694,
"rvv_bench.byteswap": 19954,
"rvv_bench.byteswap": 20017,
"rvv_bench.mandelbrot": 230851,
"rvv_bench.memcpy": 34534,
"rvv_bench.memcpy": 34718,
"rvv_bench.memset": 11501,
"rvv_bench.mergelines": 24842,
"rvv_bench.strlen": 22697,
"rvv_bench.utf8_count": 151155
"rvv_bench.utf8_count": 151165
}
62 changes: 31 additions & 31 deletions .github/designs/blastoise/t1rocketemu.json
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"asm.memcpy": 751,
"asm.mmm": 51749,
"asm.smoke": 8001,
"asm.strlen": 7986,
"asm.utf8_count": 205,
"asm.memcpy": 774,
"asm.mmm": 51794,
"asm.smoke": 8051,
"asm.strlen": 8009,
"asm.utf8_count": 232,
"codegen.vaadd_vv": 170452,
"codegen.vaadd_vx": 539363,
"codegen.vaaddu_vv": 170452,
Expand Down Expand Up @@ -499,30 +499,30 @@
"codegen.vxor_vx": 136518,
"codegen.vzext_vf2": 14020,
"codegen.vzext_vf4": 4333,
"intrinsic.conv2d_less_m2": 2498,
"intrinsic.linear_normalization": 3350,
"intrinsic.matmul": 65866,
"intrinsic.softmax": 6795,
"mlir.axpy_masked": 4048,
"mlir.conv": 125859,
"mlir.hello": 131,
"mlir.matmul": 56059,
"mlir.maxvl_tail_setvl_front": 700,
"mlir.rvv_vp_intrinsic_add": 466,
"mlir.rvv_vp_intrinsic_add_scalable": 807,
"mlir.stripmining": 8882,
"mlir.vectoradd": 13236,
"pytorch.demo": 31521,
"pytorch.matmul": 69793,
"rvv_bench.ascii_to_utf16": 677090,
"rvv_bench.ascii_to_utf32": 226918,
"rvv_bench.byteswap": 399524,
"rvv_bench.chacha20": 39957,
"rvv_bench.mandelbrot": 512683,
"rvv_bench.memcpy": 671955,
"rvv_bench.memset": 290725,
"rvv_bench.mergelines": 564159,
"rvv_bench.poly1305": 39957,
"rvv_bench.strlen": 219139,
"rvv_bench.utf8_count": 2283382
"intrinsic.conv2d_less_m2": 2550,
"intrinsic.linear_normalization": 3373,
"intrinsic.matmul": 65918,
"intrinsic.softmax": 6824,
"mlir.axpy_masked": 4098,
"mlir.conv": 125881,
"mlir.hello": 175,
"mlir.matmul": 56109,
"mlir.maxvl_tail_setvl_front": 749,
"mlir.rvv_vp_intrinsic_add": 517,
"mlir.rvv_vp_intrinsic_add_scalable": 858,
"mlir.stripmining": 8931,
"mlir.vectoradd": 13281,
"pytorch.demo": 31524,
"pytorch.matmul": 69835,
"rvv_bench.ascii_to_utf16": 690528,
"rvv_bench.ascii_to_utf32": 230915,
"rvv_bench.byteswap": 399613,
"rvv_bench.chacha20": 40010,
"rvv_bench.mandelbrot": 512751,
"rvv_bench.memcpy": 672015,
"rvv_bench.memset": 290646,
"rvv_bench.mergelines": 561433,
"rvv_bench.poly1305": 40010,
"rvv_bench.strlen": 218969,
"rvv_bench.utf8_count": 2230705
}
4 changes: 2 additions & 2 deletions .github/designs/rookidee/t1emu.json
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,8 @@
"mlir.stripmining": 27810,
"rvv_bench.ascii_to_utf16": 16070,
"rvv_bench.ascii_to_utf32": 6057,
"rvv_bench.byteswap": 43274,
"rvv_bench.memcpy": 46320,
"rvv_bench.byteswap": 43109,
"rvv_bench.memcpy": 46538,
"rvv_bench.memset": 19350,
"rvv_bench.mergelines": 38541,
"rvv_bench.strlen": 34517,
Expand Down
34 changes: 17 additions & 17 deletions .github/designs/rookidee/t1rocketemu.json
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"asm.mmm": 56295,
"asm.smoke": 7780,
"asm.mmm": 56340,
"asm.smoke": 7830,
"codegen.vaadd_vv": 129499,
"codegen.vaadd_vx": 393229,
"codegen.vaaddu_vv": 129499,
Expand Down Expand Up @@ -430,19 +430,19 @@
"codegen.vxor_vx": 98738,
"codegen.vzext_vf2": 11522,
"codegen.vzext_vf4": 3497,
"intrinsic.conv2d_less_m2": 2540,
"mlir.hello": 130,
"mlir.rvv_vp_intrinsic_add": 462,
"mlir.rvv_vp_intrinsic_add_scalable": 706,
"mlir.stripmining": 27825,
"rvv_bench.ascii_to_utf16": 678943,
"rvv_bench.ascii_to_utf32": 226997,
"rvv_bench.byteswap": 422035,
"rvv_bench.chacha20": 39957,
"rvv_bench.memcpy": 677231,
"rvv_bench.memset": 295653,
"rvv_bench.mergelines": 580218,
"rvv_bench.poly1305": 39957,
"rvv_bench.strlen": 235252,
"rvv_bench.utf8_count": 2346912
"intrinsic.conv2d_less_m2": 2592,
"mlir.hello": 174,
"mlir.rvv_vp_intrinsic_add": 513,
"mlir.rvv_vp_intrinsic_add_scalable": 757,
"mlir.stripmining": 27874,
"rvv_bench.ascii_to_utf16": 692453,
"rvv_bench.ascii_to_utf32": 231013,
"rvv_bench.byteswap": 421946,
"rvv_bench.chacha20": 40010,
"rvv_bench.memcpy": 677194,
"rvv_bench.memset": 295581,
"rvv_bench.mergelines": 577576,
"rvv_bench.poly1305": 40010,
"rvv_bench.strlen": 235082,
"rvv_bench.utf8_count": 2294279
}

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