[rtl] fix find first.

chipsalliance · Nov 15, 2024 · 1710987 · 1710987
1 parent 0237c9b
commit 1710987
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/t1/src/mask/MaskCompress.scala b/t1/src/mask/MaskCompress.scala
@@ -41,6 +41,7 @@ class MaskCompress(parameter: T1Parameter) extends Module {
   val viota    = in.bits.uop === "b000".U
   val mv       = in.bits.uop === "b010".U
   val mvRd     = in.bits.uop === "b011".U
+  val writeRD  = in.bits.uop === BitPat("b?11")
   val ffoType  = in.bits.uop === BitPat("b11?")
 
   val eew1H:           UInt      = UIntToOH(in.bits.eew)(2, 0)
@@ -196,7 +197,7 @@ class MaskCompress(parameter: T1Parameter) extends Module {
   )
 
   // todo
-  out.compressValid := (compressTailValid || (compressDeqValid && in.fire)) && !mvRd
+  out.compressValid := (compressTailValid || (compressDeqValid && in.fire)) && !writeRD
   out.groupCounter  := Mux(compress, compressWriteGroupCount, in.bits.groupCounter)
 
   when(newInstruction && ffoInstruction) {