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[perf] fill up some missing signal and clean up the PerfEvent module
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Signed-off-by: Avimitin <[email protected]>
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@Avimitin
Avimitin committed Oct 18, 2023
1 parent 9f3cd96 commit 13b3577
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Showing 7 changed files with 170 additions and 166 deletions.
24 changes: 17 additions & 7 deletions elaborator/src/PerfMonitor.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ class LoadUnitCacheLineDequeueMonitor extends IndexedPerfMonitor with ValidMonit
/**
* Monitor signals in [[v.SimpleAccessUnit]]
*/
class SimpleAccessUnitMonitor extends PerfMonitor {
class OtherUnitMonitor extends PerfMonitor {
val lsuRequestIsValid = dpiIn("SimpleAccessUnitLSURequestIsValid", Input(Bool()))

val vrfReadDataPortsIsReady = dpiIn("SimpleAccessUnitVRFReadDataPortsIsReady", Input(Bool()))
Expand All @@ -60,17 +60,21 @@ class SimpleAccessUnitMonitor extends PerfMonitor {
val vrfWritePortIsReady = dpiIn("SimpleAccessUnitVRFWritePortIsReady", Input(Bool()))
val vrfWritePortIsValid = dpiIn("SimpleAccessUnitVRFWritePortIsValid", Input(Bool()))

val currentLane = dpiIn("SimpleAccessUnitStatusTargetLane", Input(UInt(32.W)))
val statusIsWaitingFirstResponse = dpiIn("SimpleAccessUnitStatusIsWaitingFirstResponse", Input(Bool()))
val targetLane = dpiIn("SimpleAccessUnitStatusTargetLane", Input(UInt(32.W)))
val idle = dpiIn("SimpleAccessUnitIsIdle", Input(Bool()))

val s0Fire = dpiIn("SimpleAccessUnitS0Fire", Input(Bool()))
val s1Fire = dpiIn("SimpleAccessUnitS1Fire", Input(Bool()))
val s2Fire = dpiIn("SimpleAccessUnitS2Fire", Input(Bool()))
}

class SimpleAccessUnitOffsetReadResultMonitor extends IndexedPerfMonitor with ValidMonitor
class OtherUnitAccessTileLinkMonitor extends ValidMonitor with ReadyMonitor

class SimpleAccessUnitIndexedInsnOffsetsIsValidMonitor extends IndexedPerfMonitor with ValidMonitor
class OtherUnitTileLinkAckMonitor extends ValidMonitor with ReadyMonitor

class OtherUnitOffsetReadResultMonitor extends IndexedPerfMonitor with ValidMonitor

class OtherUnitIndexedInsnOffsetsIsValidMonitor extends IndexedPerfMonitor with ValidMonitor
// End of SimpleAccessUnit monitors definition


Expand Down Expand Up @@ -122,8 +126,8 @@ class LaneWriteQueueMonitor extends IndexedPerfMonitor with ValidMonitor
class LaneReadBusDequeueMonitor extends IndexedPerfMonitor with ValidMonitor

class CrossLaneMonitor extends IndexedPerfMonitor {
val crossLaneReadValid = dpiIn("crossLaneReadValid", Input(Bool()))
val crossLaneWriteValid = dpiIn("crossLaneWriteValid", Input(Bool()))
val readValid = dpiIn("crossLaneReadValid", Input(Bool()))
val writeValid = dpiIn("crossLaneWriteValid", Input(Bool()))
}

class LaneReadBusDataMonitor extends IndexedPerfMonitor with ValidMonitor
Expand Down Expand Up @@ -157,6 +161,12 @@ class VDataResultMonitor extends ValidMonitor

class VLaneReadyMonitor extends IndexedPerfMonitor with ReadyMonitor

class VExecutionReadyMonitor extends PerfMonitor with ReadyMonitor

class VInsnRawReadyMonitor extends PerfMonitor with ReadyMonitor

class VSlotReadyMonitor extends PerfMonitor with ReadyMonitor

class VSlotStatIdleMonitor extends IndexedPerfMonitor {
val idle = dpiIn("idle", Input(Bool()))
}
Expand Down
58 changes: 40 additions & 18 deletions elaborator/src/TestBench.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ import tilelink.TLChannelD
class TestBench(generator: SerializableModuleGenerator[V, VParameter]) extends RawModule {
val clock = Wire(Clock())
val reset = Wire(Bool())
val dut = withClockAndReset(clock, reset)(Module(generator.module()))
val dut: V = withClockAndReset(clock, reset)(Module(generator.module()))
withClockAndReset(clock, reset) {
// val coverModule = Module(new CoverModule(dut))
val monitor = Module(new Monitor(dut))
Expand Down Expand Up @@ -85,29 +85,39 @@ class TestBench(generator: SerializableModuleGenerator[V, VParameter]) extends R
/**
* [[v.SimpleAccessUnit]] related probe connection
*/
val simpleAccessUnitMonitor = Module(new SimpleAccessUnitMonitor)
simpleAccessUnitMonitor.clock.ref := clock.asBool
simpleAccessUnitMonitor.lsuRequestIsValid.ref := read(bore(dut.lsu.otherUnit.lsuRequestValidProbe))
simpleAccessUnitMonitor.vrfReadDataPortsIsReady.ref := read(bore(dut.lsu.otherUnit.vrfReadDataPortsValidProbe))
simpleAccessUnitMonitor.vrfReadDataPortsIsValid.ref := read(bore(dut.lsu.otherUnit.vrfReadDataPortsReadyProbe))
simpleAccessUnitMonitor.maskSelectIsValid.ref := read(bore(dut.lsu.otherUnit.maskSelectValidProbe))
simpleAccessUnitMonitor.vrfWritePortIsReady.ref := read(bore(dut.lsu.otherUnit.vrfWritePortIsReadyProbe))
simpleAccessUnitMonitor.vrfWritePortIsValid.ref := read(bore(dut.lsu.otherUnit.vrfWritePortIsValidProbe))
simpleAccessUnitMonitor.currentLane.ref := read(bore(dut.lsu.otherUnit.currentLaneProbe))
simpleAccessUnitMonitor.statusIsWaitingFirstResponse.ref := read(bore(dut.lsu.otherUnit.statusIsWaitingFirstResponseProbe))
simpleAccessUnitMonitor.s0Fire.ref := read(bore(dut.lsu.otherUnit.s0FireProbe))
simpleAccessUnitMonitor.s1Fire.ref := read(bore(dut.lsu.otherUnit.s1FireProbe))
simpleAccessUnitMonitor.s2Fire.ref := read(bore(dut.lsu.otherUnit.s2FireProbe))
val otherUnitMonitor = Module(new OtherUnitMonitor)
otherUnitMonitor.clock.ref := clock.asBool
otherUnitMonitor.lsuRequestIsValid.ref := read(bore(dut.lsu.otherUnit.lsuRequestValidProbe))
otherUnitMonitor.vrfReadDataPortsIsReady.ref := read(bore(dut.lsu.otherUnit.vrfReadDataPortsValidProbe))
otherUnitMonitor.vrfReadDataPortsIsValid.ref := read(bore(dut.lsu.otherUnit.vrfReadDataPortsReadyProbe))
otherUnitMonitor.maskSelectIsValid.ref := read(bore(dut.lsu.otherUnit.maskSelectValidProbe))
otherUnitMonitor.vrfWritePortIsReady.ref := read(bore(dut.lsu.otherUnit.vrfWritePortIsReadyProbe))
otherUnitMonitor.vrfWritePortIsValid.ref := read(bore(dut.lsu.otherUnit.vrfWritePortIsValidProbe))
otherUnitMonitor.targetLane.ref := read(bore(dut.lsu.otherUnit.targetLaneProbe))
otherUnitMonitor.idle.ref := read(bore(dut.lsu.otherUnit.statusIdleProbe))
otherUnitMonitor.s0Fire.ref := read(bore(dut.lsu.otherUnit.s0FireProbe))
otherUnitMonitor.s1Fire.ref := read(bore(dut.lsu.otherUnit.s1FireProbe))
otherUnitMonitor.s2Fire.ref := read(bore(dut.lsu.otherUnit.s2FireProbe))

val otherUnitAccessTileLinkMonitor = Module(new OtherUnitAccessTileLinkMonitor)
otherUnitAccessTileLinkMonitor.clock.ref := clock.asBool
otherUnitAccessTileLinkMonitor.isValid.ref := read(bore(dut.lsu.otherUnit.accessTileLinkValidProbe))
otherUnitAccessTileLinkMonitor.isReady.ref := read(bore(dut.lsu.otherUnit.accessTileLinkReadyProbe))

val otherUnitTileLinkAckMonitor = Module(new OtherUnitTileLinkAckMonitor)
otherUnitTileLinkAckMonitor.clock.ref := clock.asBool
otherUnitTileLinkAckMonitor.isValid.ref := read(bore(dut.lsu.otherUnit.tileLinkAckValidProbe))
otherUnitTileLinkAckMonitor.isReady.ref := read(bore(dut.lsu.otherUnit.tileLinkAckReadyProbe))

dut.lsu.otherUnit.offsetReadResultValidProbe.zipWithIndex.foreach({ case(probe, i) =>
val monitor = Module(new SimpleAccessUnitOffsetReadResultMonitor)
val monitor = Module(new OtherUnitOffsetReadResultMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U
monitor.isValid.ref := read(bore(probe))
})

dut.lsu.otherUnit.indexedInsturctionOffsetsIsValidProbe.zipWithIndex.foreach({ case(probe, i) =>
val monitor = Module(new SimpleAccessUnitIndexedInsnOffsetsIsValidMonitor)
val monitor = Module(new OtherUnitIndexedInsnOffsetsIsValidMonitor)
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U
monitor.isValid.ref := read(bore(probe))
Expand Down Expand Up @@ -227,8 +237,8 @@ class TestBench(generator: SerializableModuleGenerator[V, VParameter]) extends R
monitor.clock.ref := clock.asBool
monitor.index.ref := i.U

monitor.crossLaneReadValid.ref := read(bore(lane.crossLaneReadValidProbe))
monitor.crossLaneWriteValid.ref := read(bore(lane.crossLaneWriteValidProbe))
monitor.readValid.ref := read(bore(lane.crossLaneReadValidProbe))
monitor.writeValid.ref := read(bore(lane.crossLaneWriteValidProbe))
}
{
val monitor = Module(new LaneReadBusDataMonitor)
Expand Down Expand Up @@ -305,6 +315,18 @@ class TestBench(generator: SerializableModuleGenerator[V, VParameter]) extends R
vSelectffoIndexMonitor.clock.ref := clock.asBool
vSelectffoIndexMonitor.isValid.ref := read(bore(dut.selectffoIndexValidProbe))

val vExecutionReadyMonitor = Module(new VExecutionReadyMonitor)
vExecutionReadyMonitor.clock.ref := clock.asBool
vExecutionReadyMonitor.isReady.ref := read(bore(dut.executionReadyProbe))

val vInsnRawReadyMonitor = Module(new VInsnRawReadyMonitor)
vInsnRawReadyMonitor.clock.ref := clock.asBool
vInsnRawReadyMonitor.isReady.ref := read(bore(dut.insnRAWReadyProbe))

val vSlotReadyMonitor = Module(new VSlotReadyMonitor)
vSlotReadyMonitor.clock.ref := clock.asBool
vSlotReadyMonitor.isReady.ref := read(bore(dut.slotReadyProbe))

dut.laneReadyProbe.zipWithIndex.foreach({ case(probe, i) =>
val monitor = Module(new VLaneReadyMonitor)
monitor.clock.ref := clock.asBool
Expand Down
45 changes: 0 additions & 45 deletions elaborator/src/VerificationModule.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -153,49 +153,4 @@ class VerificationModule(dut: V) extends RawModule {
poke.dReady.ref := tapAndRead(bundle.d.ready)
bore(bundle.a.ready) := poke.aReady.ref
}

if (false) {
val perfEvent = Module(new PerfEvent(PerfEventParameter(latPeekIssue, dut.parameter)))
perfEvent.clock.ref := genClock
perfEvent.instructionEnqValid.ref := tapAndRead(dut.requestRegDequeue.valid)
perfEvent.instructionEnqReady.ref := tapAndRead(dut.requestRegDequeue.ready)
perfEvent.executionReady.ref := tapAndRead(dut.executionReady)
perfEvent.slotReady.ref := tapAndRead(dut.slotReady)
perfEvent.instructionRAWReady.ref := tapAndRead(dut.instructionRAWReady)

dut.laneVec.zipWithIndex.foreach { case (lane, index) =>
perfEvent.slotShifterEnqueue(index) zip lane.slotEnqueueFire.map(tapAndRead(_)) foreach {case (s, i) => s.ref := i}
}

// lsu store unit
perfEvent.storeUnitIdle.ref := tapAndRead(dut.lsu.storeUnit.status.idle)
dut.lsu.storeUnit.status.releasePort.zip(perfEvent.storeUnitReleasePort).foreach {case (d, r) => r.ref := tapAndRead(d)}
dut.lsu.storeUnit.vrfReadDataPorts.zip(perfEvent.storeUnitReadVrfValid).foreach {case(d, r) => r.ref := tapAndRead(d.valid)}
dut.lsu.storeUnit.vrfReadDataPorts.zip(perfEvent.storeUnitReadVrfReady).foreach {case(d, r) => r.ref := tapAndRead(d.ready)}
perfEvent.vrfReadyToStore.ref := tapAndRead(dut.lsu.storeUnit.vrfReadyToStore)
dut.lsu.storeUnit.tlPortA.zip(perfEvent.storeUnitAccessTileLinkValid).foreach {case (d, r) => r.ref := tapAndRead(d.valid)}
dut.lsu.storeUnit.tlPortA.zip(perfEvent.storeUnitAccessTileLinkReady).foreach {case (d, r) => r.ref := tapAndRead(d.ready)}

// lsu load unit
perfEvent.loadUnitIdle.ref := tapAndRead(dut.lsu.loadUnit.status.idle)
perfEvent.writeReadyForLsu.ref := tapAndRead(dut.lsu.loadUnit.writeReadyForLsu)
perfEvent.loadUnitAccessTileLinkValid.ref := tapAndRead(dut.lsu.loadUnit.tlPortA.valid)
perfEvent.loadUnitAccessTileLinkReady.ref := tapAndRead(dut.lsu.loadUnit.tlPortA.ready)
dut.lsu.loadUnit.tlPortD.zip(perfEvent.loadUnitTileLinkAckValid).foreach {case (d, r) => r.ref := tapAndRead(d.valid)}
dut.lsu.loadUnit.tlPortD.zip(perfEvent.loadUnitTileLinkAckReady).foreach {case (d, r) => r.ref := tapAndRead(d.ready)}
dut.lsu.loadUnit.vrfWritePort.zip(perfEvent.loadUnitWriteVrfValid).foreach {case (d, r) => r.ref := tapAndRead(d.valid)}
dut.lsu.loadUnit.vrfWritePort.zip(perfEvent.loadUnitWriteVrfReady).foreach {case (d, r) => r.ref := tapAndRead(d.ready)}

// lsu other unit
perfEvent.otherUnitIdle.ref := tapAndRead(dut.lsu.otherUnit.status.idle)
perfEvent.otherUnitReadVrfValid.ref := tapAndRead(dut.lsu.otherUnit.vrfReadDataPorts.valid)
perfEvent.otherUnitReadVrfReady.ref := tapAndRead(dut.lsu.otherUnit.vrfReadDataPorts.ready)
perfEvent.otherUnitAccessTileLinkValid.ref := tapAndRead(dut.lsu.otherUnit.tlPort.a.valid)
perfEvent.otherUnitAccessTileLinkReady.ref := tapAndRead(dut.lsu.otherUnit.tlPort.a.ready)
perfEvent.otherUnitTileLinkAckValid.ref := tapAndRead(dut.lsu.otherUnit.tlPort.d.valid)
perfEvent.otherUnitTileLinkAckReady.ref := tapAndRead(dut.lsu.otherUnit.tlPort.d.ready)
perfEvent.otherUnitWriteVrfValid.ref := tapAndRead(dut.lsu.otherUnit.vrfWritePort.valid)
perfEvent.otherUnitWriteVrfReady.ref := tapAndRead(dut.lsu.otherUnit.vrfWritePort.ready)
perfEvent.otherUnitAccessVrfTargetLane.ref := tapAndRead(dut.lsu.otherUnit.status.targetLane)
}
}
66 changes: 0 additions & 66 deletions elaborator/src/dpi/PerfEvent.scala
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