[difftest] add t1_cosim_refresh dpi to support refresh the last com…

…mit cycle controled by rtl

difftest/dpi_t1emu/src/dpi.rs

@@ -241,6 +241,13 @@ unsafe extern "C" fn t1_cosim_watchdog() -> u8 {
   TARGET.with(|driver| driver.watchdog())
 }
 
+#[no_mangle]
+unsafe extern "C" fn t1_cosim_refresh() {
+  TARGET.with(|driver| {
+    driver.last_commit_cycle = crate::get_t();
+  })
+}
+
 /// evaluate at instruction queue is not empty
 /// arg issue will be type cast from a struct to svBitVecVal*(uint32_t*)
 #[no_mangle]

difftest/dpi_t1emu/src/drive.rs

@@ -108,7 +108,7 @@ pub(crate) struct Driver {
   max_commit_interval: u64,
 
   // driver state
-  last_commit_cycle: u64,
+  pub(crate) last_commit_cycle: u64,
   issued: u64,
   vector_lsu_count: u8,
 
@@ -325,6 +325,7 @@ impl Driver {
     self.shadow_mem.apply_writes(&se.mem_access_record);
 
     self.spike_runner.commit_queue.pop_back();
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
   }
 

difftest/dpi_t1rocketemu/src/dpi.rs

@@ -313,6 +313,14 @@ unsafe extern "C" fn t1_cosim_watchdog() -> u8 {
   TARGET.with(|driver| driver.watchdog())
 }
 
+/// update last_commit_cycle to current cycle
+#[no_mangle]
+unsafe extern "C" fn t1_cosim_refresh() {
+  TARGET.with(|driver| {
+    driver.last_commit_cycle = crate::get_t();
+  })
+}
+
 #[no_mangle]
 unsafe extern "C" fn get_resetvector(resetvector: *mut c_longlong) {
   TARGET.with_optional(|driver| {

difftest/dpi_t1rocketemu/src/drive.rs

@@ -33,7 +33,7 @@ pub(crate) struct Driver {
   pub(crate) e_entry: u64,
 
   max_commit_interval: u64,
-  last_commit_cycle: u64,
+  pub(crate) last_commit_cycle: u64,
 
   shadow_bus: ShadowBus,
 
@@ -134,6 +134,7 @@ impl Driver {
     let size = 1 << arsize;
     let data = self.shadow_bus.read_mem_axi(addr, size, self.dlen / 8);
     let data_hex = hex::encode(&data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_read_high_bandwidth (addr={addr:#x}, size={size}, data={data_hex})",
@@ -152,6 +153,7 @@ impl Driver {
     let size = 1 << awsize;
     self.shadow_bus.write_mem_axi(addr, size, self.dlen / 8, &strobe, data);
     let data_hex = hex::encode(data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_write_high_bandwidth (addr={addr:#x}, size={size}, data={data_hex})",
@@ -164,6 +166,7 @@ impl Driver {
     assert!(size <= 4);
     let data = self.shadow_bus.read_mem_axi(addr, size, 4);
     let data_hex = hex::encode(&data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_read_high_outstanding (addr={addr:#x}, size={size}, data={data_hex})",
@@ -182,6 +185,7 @@ impl Driver {
     let size = 1 << awsize;
     self.shadow_bus.write_mem_axi(addr, size, 4, strobe, data);
     let data_hex = hex::encode(data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_write_high_outstanding (addr={addr:#x}, size={size}, data={data_hex})",
@@ -194,6 +198,7 @@ impl Driver {
     let bus_size = if size == 32 { 32 } else { 4 };
     let data = self.shadow_bus.read_mem_axi(addr, size, bus_size);
     let data_hex = hex::encode(&data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_read_load_store (addr={addr:#x}, size={size}, data={data_hex})",
@@ -213,6 +218,7 @@ impl Driver {
     let bus_size = if size == 32 { 32 } else { 4 };
     self.shadow_bus.write_mem_axi(addr, size, bus_size, strobe, data);
     let data_hex = hex::encode(data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
 
     trace!(