[rtl] fix mask update.

chipsalliance · Dec 26, 2024 · 0dab960 · 0dab960
1 parent 93fcb10
commit 0dab960
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -965,7 +965,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     maskSelectSew      := Mux1H(maskControlReqSelect, maskControlVec.map(_.sew))
     maskControlDataDeq := slotMaskRequestVec.zipWithIndex.map { case (req, index) =>
       val slotIndex       = slotControl(index).laneRequest.instructionIndex
-      val hitMaskControl  = VecInit(maskControlVec.map(_.index === slotIndex)).asUInt
+      val hitMaskControl  = VecInit(maskControlVec.map(c => c.index === slotIndex && c.controlValid)).asUInt
       val dataValid       = Mux1H(hitMaskControl, maskControlVec.map(_.dataValid))
       val data            = Mux1H(hitMaskControl, maskControlVec.map(_.maskData))
       val group           = Mux1H(hitMaskControl, maskControlVec.map(_.group))