[difftest] add support for compressed loads and stores

difftest/spike_rs/src/spike_event.rs

@@ -202,12 +202,12 @@ impl SpikeEvent {
 
   // check whether the instruction is a scalar load
   pub fn is_load(&self) -> bool {
-    self.opcode() == 0b0000011
+    self.opcode() == 0b0000011 || self.is_cl()
   }
 
   // check whether the instruction is a scalar store
   pub fn is_store(&self) -> bool {
-    self.opcode() == 0b0100011
+    self.opcode() == 0b0100011 || self.is_cw()
   }
 
   pub fn is_whole(&self) -> bool {
@@ -241,6 +241,24 @@ impl SpikeEvent {
       && (self.width() == 0b001)
   }
 
+  pub fn c_op(&self) -> u32 {
+    clip(self.inst_bits, 0, 1)
+  }
+
+  pub fn c_func3(&self) -> u32 {
+    clip(self.inst_bits, 13, 15)
+  }
+
+  pub fn is_cl(&self) -> bool {
+    ( self.c_op() == 0b00 && self.c_func3() & 0b100 == 0 ) || /* c.lw */
+    ( self.c_op() == 0b10 && self.c_func3() & 0b100 == 0 ) /* c.lwsp */
+  }
+
+  pub fn is_cw(&self) -> bool {
+    ( self.c_op() == 0b00 && self.c_func3() & 0b100 != 0 ) || /* c.sw */
+    ( self.c_op() == 0b10 && self.c_func3() & 0b100 != 0 ) /* c.swsp */
+  }
+
   pub fn vlmul(&self) -> u32 {
     clip(self.vtype, 0, 2)
   }