[rtl] fix assert logic.

chipsalliance · Aug 22, 2024 · 09d4975 · 09d4975
1 parent a4c4278
commit 09d4975
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -762,7 +762,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
         UIntToOH(executionUnit.responseIndex(parameter.instructionIndexBits - 2, 0)),
         0.U(parameter.chainingSize.W)
       )
-      AssertProperty(BoolSequence(executionUnit.dequeue.valid && stage2.dequeue.valid))
+      AssertProperty(BoolSequence(!executionUnit.dequeue.valid || stage2.dequeue.valid))
       stage3.enqueue.valid := executionUnit.dequeue.valid
       executionUnit.dequeue.ready := stage3.enqueue.ready
       stage2.dequeue.ready := executionUnit.dequeue.fire