[rtl] fix mask select in mask unit.

chipsalliance · Nov 20, 2024 · 056a50d · 056a50d
1 parent 97ae813
commit 056a50d
Showing 1 changed file with 2 additions and 5 deletions.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -434,7 +434,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val slideAddressGen: SlideIndexGen = Module(new SlideIndexGen(parameter))
   slideAddressGen.newInstruction := instReq.valid & instReq.bits.vl.orR
   slideAddressGen.instructionReq := instReg
-  slideAddressGen.slideMaskInput := cutUInt(v0.asUInt, 8)(slideAddressGen.slideGroupOut)
+  slideAddressGen.slideMaskInput := cutUInt(v0.asUInt, parameter.laneNumber)(slideAddressGen.slideGroupOut)
 
   val firstRequest:    Bool = RegInit(false.B)
   val viotaCounterAdd: Bool = Wire(Bool())
@@ -519,10 +519,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   ) & Fill(parameter.laneNumber, validExecuteGroup)
 
   // handle mask
-  val readMaskSelect:      UInt =
-    (executeGroup >> log2Ceil(parameter.datapathWidth / parameter.laneNumber)).asUInt
-  val readMaskInput:       UInt = cutUInt(v0.asUInt, parameter.maskGroupWidth)(readMaskSelect)
-  val selectReadStageMask: UInt = cutUIntBySize(readMaskInput, 4)(executeGroup(1, 0))
+  val selectReadStageMask: UInt = cutUInt(v0.asUInt, parameter.laneNumber)(executeGroup)
   val readMaskCorrection:  UInt =
     Mux(instReg.maskType, selectReadStageMask, -1.S(parameter.laneNumber.W).asUInt) &
       vlBoundaryCorrection