[temp] add SRAMBlackbox(and need to be moved to chisel upstream)

chipsalliance · Nov 29, 2024 · 03b2ece · 03b2ece
1 parent ea03c82
commit 03b2ece
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Showing 6 changed files with 864 additions and 2 deletions.
diff --git a/rocketv/src/HellaCache.scala b/rocketv/src/HellaCache.scala
@@ -25,7 +25,6 @@ import chisel3.util.{
   PriorityEncoderOH,
   PriorityMux,
   RegEnable,
-  SRAM,
   SRAMInterface,
   UIntToOH
 }
@@ -40,6 +39,7 @@ import org.chipsalliance.amba.axi4.bundle.{
   W
 }
 import org.chipsalliance.dwbb.stdlib.queue.{Queue, QueueIO}
+import chisel3.hack.util.SRAM
 
 object HellaCacheParameter {
   implicit def bitSetP: upickle.default.ReadWriter[BitSet] = upickle.default

diff --git a/rocketv/src/ICache.scala b/rocketv/src/ICache.scala
@@ -12,6 +12,7 @@ import chisel3.util.random.LFSR
 import chisel3.util._
 import org.chipsalliance.amba.axi4.bundle.{AXI4BundleParameter, AXI4ROIrrevocable, AXI4RWIrrevocable}
 import org.chipsalliance.dwbb.stdlib.queue.Queue
+import chisel3.hack.util.SRAM
 
 case class ICacheParameter(
   useAsyncReset: Boolean,

diff --git a/rocketv/src/PTW.scala b/rocketv/src/PTW.scala
@@ -22,11 +22,11 @@ import chisel3.util.{
   PriorityEncoder,
   PriorityEncoderOH,
   RegEnable,
-  SRAM,
   SRAMInterface,
   UIntToOH,
   Valid
 }
+import chisel3.hack.util.SRAM
 
 object PTWParameter {
   implicit def rwP: upickle.default.ReadWriter[PTWParameter] = upickle.default.macroRW[PTWParameter]