Pass design parameters by verilog parameters #1069
Triggered via pull request
December 7, 2024 17:14
FanShupei
Status
Success
Total duration
1h 4m 52s
Artifacts
–
vcs.yml
on: pull_request
Generate test plan
7s
Matrix: Build VCS Emulators
Matrix: Run VCS
Report VCS CI result
56s