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Build(deps): Bump third_party/black_parrot_tools from 2c2df67 to d6cbe09 #6012

Build(deps): Bump third_party/black_parrot_tools from 2c2df67 to d6cbe09

Build(deps): Bump third_party/black_parrot_tools from 2c2df67 to d6cbe09 #6012

Triggered via pull request November 7, 2024 07:34
Status Success
Total duration 57m 39s
Artifacts 49

main.yml

on: pull_request
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 28s
Style check
Verify README Correctness (Installation From Sources)
42m 7s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 7s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
11m 36s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
37m 29s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
47m 25s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
4m 58s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
14m 44s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
38m 21s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
39m 6s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 31s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
2m 0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
2m 12s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

4 warnings
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
292 MB
binaries-package
23.1 MB
binaries-plugin
41.6 MB
binaries-pysynlig
652 MB
binaries-release
41.9 MB
bp_e_bp_unicore_cfg.edif
3.9 MB
bsg-logs
5.56 MB
bsg-outputs
1.72 MB
formal-verification-logs-simple
18.1 MB
formal-verification-logs-sv2v
62.7 MB
formal-verification-logs-yosys
50.4 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit
105 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
5.09 MB
opentitan-logs-quick
1.52 MB
plots_binaries-asan
52 KB
plots_binaries-package
31.2 KB
plots_binaries-plugin
31 KB
plots_binaries-pysynlig
66.4 KB
plots_binaries-release
32.4 KB
plots_blackparrot_synth_asic
232 KB
plots_blackparrot_synth_xilinx
96.1 KB
plots_blackparrot_synth_xilinx_python
227 KB
plots_build_tools
79.2 KB
plots_formal_verification_simple
113 KB
plots_formal_verification_sv2v
116 KB
plots_formal_verification_yosys
95 KB
plots_ibex_synth
45 KB
plots_ibex_synth_f4pga
81.9 KB
plots_opentitan_9d82960888_synth
192 KB
plots_opentitan_parse_report_full
81.9 KB
plots_opentitan_parse_report_quick
45.3 KB
plots_opentitan_synth
250 KB
plots_tests_asan_read_systemverilog
220 KB
plots_tests_asan_read_uhdm
166 KB
plots_tests_plugin_read_systemverilog
34.9 KB
plots_tests_plugin_read_uhdm
33.2 KB
plots_tests_release_read_systemverilog
35.1 KB
plots_tests_release_read_uhdm
32.5 KB
plots_veer_synth
35.5 KB
python_bp_e_bp_unicore_cfg.edif
3.9 MB
results_parsing_tests_asan_read_systemverilog
1.6 MB
results_parsing_tests_asan_read_uhdm
1.81 MB
results_parsing_tests_plugin_read_systemverilog
1.53 MB
results_parsing_tests_plugin_read_uhdm
1.78 MB
results_parsing_tests_release_read_systemverilog
1.49 MB
results_parsing_tests_release_read_uhdm
1.73 MB
tools
39.1 MB
top_artya7.bit
121 KB