Build(deps): Bump third_party/black_parrot_tools from `2c2df67` to `d6cbe09` #6012

Job	Run time
Build Synlig Release	5m 1s
Build Plugin	4m 11s
Build Synlig (ASAN)	7m 38s
Build Package	4m 43s
Build PySynlig	9m 56s
Build tools	10m 47s
Emit Workflow Info	0s
Style check	1m 28s
Verify README Correctness (Installation From Sources)	42m 7s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 31s
Large Designs Tests / Ibex (Vivado synthesis)	6m 7s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	14m 44s
Large Designs Tests / Black Parrot (ASIC synthesis)	38m 21s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 36s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	37m 29s
Large Designs Tests / Opentitan (synthesis)	47m 25s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 10s
Large Designs Tests / VeeR-EH1 (synthesis)	4m 58s
Large Designs Tests / Opentitan parsing (quick)	6m 16s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	39m 6s
Parsing Tests / Test read_systemverilog release	4m 23s
Parsing Tests / Test read_uhdm release	4m 13s
Parsing Tests / Test read_systemverilog plugin	4m 23s
Parsing Tests / Test read_uhdm plugin	4m 15s
Parsing Tests / Test read_systemverilog asan	35m 9s
Parsing Tests / Test read_uhdm asan	25m 33s
Formal Verification Tests / simple	17m 3s
Formal Verification Tests / sv2v	17m 4s
Formal Verification Tests / yosys	14m 31s
Parsing Tests / Summary Generation	2m 12s
Parsing Tests / Generate AST diff	2m 0s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 21m 20s

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