Build(deps): Bump third_party/sby from `62d1708` to `117fb26` (#2611) #5971

Job	Run time
Style check	1m 42s
Build tools	10m 51s
Build Synlig Release	4m 46s
Emit Workflow Info	0s
Build Plugin	4m 17s
Verify README Correctness (Installation From Sources)	42m 38s
Build Synlig (ASAN)	8m 34s
Build Package	5m 9s
Build PySynlig	10m 20s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	25m 8s
Large Designs Tests / Ibex (Vivado synthesis)	6m 12s
Large Designs Tests / Opentitan (synthesis)	50m 11s
Large Designs Tests / Ibex (F4PGA synthesis)	10m 53s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 25s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	12m 3s
Large Designs Tests / Opentitan parsing (quick)	5m 39s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	32m 47s
Large Designs Tests / Black Parrot (ASIC synthesis)	37m 17s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 9s
Parsing Tests / Test read_systemverilog release	4m 27s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 8s
Parsing Tests / Test read_uhdm release	4m 22s
Parsing Tests / Test read_systemverilog plugin	4m 28s
Parsing Tests / Test read_uhdm plugin	4m 12s
Parsing Tests / Test read_systemverilog asan	34m 45s
Parsing Tests / Test read_uhdm asan	25m 34s
Formal Verification Tests / simple	14m 25s
Formal Verification Tests / sv2v	15m 15s
Formal Verification Tests / yosys	11m 55s
Parsing Tests / Summary Generation	1m 31s
Parsing Tests / Generate AST diff	0s
Release Package	11s
Verify README Correctness (Download And Run Release)	1m 45s
	6h 54m 59s

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