Build(deps): Bump third_party/surelog from `5f6e20e` to `fbbe26e` #5853

Job	Run time
Build tools	11m 18s
Build Synlig Release	4m 55s
Emit Workflow Info	0s
Build Plugin	4m 48s
Style check	2m 1s
Build Synlig (ASAN)	9m 5s
Test "Installation from source" from README	33m 18s
Upload GHA event file	3s
Test With Bundled Yosys	3m 27s
Large Designs Tests / Ibex (Vivado synthesis)	6m 10s
Large Designs Tests / Ibex (F4PGA synthesis)	10m 55s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	29m 52s
Large Designs Tests / Opentitan (synthesis)	52m 4s
Large Designs Tests / Black Parrot (ASIC synthesis)	36m 6s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 10s
Large Designs Tests / Opentitan parsing (full/top-down)	16m 13s
Large Designs Tests / Opentitan parsing (quick)	13m 7s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 24s
Parsing Tests / SystemVerilog Plugin	41m 45s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	9m 59s
Parsing Tests / Surelog	31m 3s
Formal Verification Tests / simple	18m 40s
Formal Verification Tests / sv2v	15m 29s
Formal Verification Tests / yosys	14m 36s
Parsing Tests / Summary Generation	1m 40s
Parsing Tests / Generate AST diff	5m 12s
Release Package	0s
	6h 33m 20s

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